BDD‐based synthesis for mixed CMOS/PTL logic

Abstract

SUMMARYPower consumption and performance are two important design constraints for logic synthesis in design automation. In this paper, we propose an efficient synthesis algorithm to minimize power dissipation and optimize performance of the given digital circuits by constructing a binary decision diagram (BDD) whose nodes can be implemented by CMOS logics and pass-transistor logics (PTL) in a cell library.For BDD mapped circuits, the conventional synthesis algorithms need three cells: the CMOS cell, PTL cell, and CMOS remapping pattern. In the proposed synthesis algorithm, we first refine the cell library structure to two kinds of cells: PTL and CMOS cells. Next, a new algorithm is presented to select the suitable cells so that the areas and power dissipation can be decreased when the logic functions of the given digital circuits are mapped into BDD. The efficiency of this algorithm has been shown in the experimental results.

Shared reduced ordered binary decision diagram‐based thermal‐aware network synthesis

“…The binary decision diagram (BDD) is a cutting-edge logic decomposition technique for manipulating Boolean functions according to specified optimization criteria. 1 A root node and two terminal nodes make up the decision diagram. The true and complimentary forms are represented by terminal nodes, while intermediary nodes form a canonical structure based on a directly acyclic graph (DAG) with the variables of the Boolean function.…”

“…The binary decision diagram (BDD) is a cutting‐edge logic decomposition technique for manipulating Boolean functions according to specified optimization criteria 1 . A root node and two terminal nodes make up the decision diagram.…”

Performance Analysis of Reversed Binary Decision Diagram Pass Transistor Logic Synthesis

“…Ref. [16] proposes an efficient synthesis algorithm to minimize power dissipation and optimize performance of the given digital circuits. It is done by constructing BDD whose nodes can be implemented by CMOS logics and PTLs in a cell library.…”

“…Binary decision diagrams (BDDs) are state-of-art data structures for the representation and manipulation of Boolean functions in the area of VLSI CAD [3][4][5]. Forward BDDs have been studied in logic synthesis because they allow for aspects of circuit synthesis and technology mapping [4,5,[8][9][10][11]16] to be combined. Because of the well-developed logic synthesis methods in static Complementary Metal Oxide Semiconductor (CMOS) technology, CMOS has been used in the realization of VLSI circuits.…”