Shared reduced ordered binary decision diagram‐based thermal‐aware network synthesis

Abstract

Summary In this work, a multi‐objective algorithm based on nondominated sorting genetic algorithm‐II (NSGA‐II) for thermal‐aware realization of a combinational logic network has been implemented. Input variable ordering of shared reduced ordered binary decision diagram (SROBDD) is done using NSGA‐II such that resulting combinational circuit generates low hotspots by suitable power density distribution. Simultaneous co‐optimization among area, power, and temperature is important in the higher levels of electronic circuit design to reduce the cooling cost. Using a multi‐objective algorithm (NSGA‐II), an effort is made to decrease the temperature by co‐optimization between the power density, area, and power simultaneously. Microelectronics Center of North Carolina (MCNC) benchmark circuits are tested using the proposed approach and an improvement of 13.65% in the silicon area and up to 10% in power dissipation, and 2.72% peak temperature reduction is reported in comparison to existing literature. HotSpot tool and Cadence Innovus are used to determine the peak temperature, actual silicon chip area, and power dissipation of algorithmic optimized solutions.