A survey for pass-transistor logic technologies-recent researches and developments and future prospects

Taki, Kazuo

doi:10.1109/aspdac.1998.669450

Cited by 13 publications

(4 citation statements)

References 71 publications

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“…This errand researches how circuits subject to GNRFET (, a creating semiconductor innovation. [2] The yearning to upgrade the structure estimations of execution, power, area, cost, and time to promote (opportunity cost) has not changed since the birthplace of the IC business. [3] In all honesty, Moore's Law is connected to propelling those boundaries.…”

Section: Introductionmentioning

confidence: 99%

High Performance Mixed Logic Decoders using MOS like GNRFET in 22nm Technology

Arora

Tripathi²

2022

J. Phys.: Conf. Ser.

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Graphene nano ribbon field effect transistor is an emerging field of research in VLSI technology beyond 32nm. VLSI main motive is to reduce power consumption and other parameters such as delay, PDP (power delay product) to improve the efficiency. This article discusses the requirement for high-performance applications that use little power. However, employing low-power devices for high-rank applications such as microprocessors, digital signal processors, and static random-access memory (SRAM) is very challenging. In the field of memory design and logical circuit design, it is well recognised that the Decoder plays a crucial role. As part of the planned work in 22nm technology, a technique has been developed for evaluating the parameters Power delay product, Energy delay product, Power consumption, and Delay on 14T and 15T based employing 2 to 4 decoders based on MOSFET and GNRFET. So, the final proposed circuit is obtained by application of decoders with the use of GNRFET while improving the performance parameters.

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Section: Introductionmentioning

confidence: 99%

High Performance Mixed Logic Decoders using MOS like GNRFET in 22nm Technology

Arora

Tripathi²

2022

J. Phys.: Conf. Ser.

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“…Decoders and multiplexers exhibit a significant role in static random access memory (SRAM) architectures and computer components. The combination of decoders and multiplexers is useful in SRAM architecture for address decoding and column multiplexers [1]. However, as the performance is considered, the type and choice of logic style and supply voltage are also important [2].…”

Section: Introductionmentioning

confidence: 99%

“…The combination of various logic styles in a single circuit results in good improvement in speed, power dissipation and area. A literature survey showed that stacked transistors are increasingly used as the complexity of CMOS circuits increases [1]. Dual value logic (DL) reduces the overhead of stacked transistors to some extent [11].…”

Section: Introductionmentioning

confidence: 99%

A 16 nm FinFET circuit with triple function as digital multiplexer, active-high and active-low output decoder for high-performance SRAM architecture

Battini¹,

Sivani²

2022

Semicond. Sci. Technol.

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This paper presents a FinFET based Single Circuit (FSC) used to realize Active-High output Decoder (AHD), Active-Low output Decoder (ALD), and Digital Multiplexer. The input signal is traversed through a single transmission gate irrespective of the size of FSC is the uniqueness of the proposed multiplexer. The new architectures of FSC use an equal number of n-FinFET and p-FinFET devices, requiring few transistors compared to CMOS designs. Three novel circuits are created using various logic styles following the same architecture. The FSC is compared with the similar circuits, and on average, the results of power dissipation and delay in the worst case show that FSC is better by 14\%, and 18\%, respectively. An FSC is created and extensively simulated at 16nm FinFET technology using Eldo software. All the circuits are designed for 0.75V, 1V, and 1.25V and are stimulated with multiple input frequencies. The proposed circuit is best suitable for row address decoders and column multiplexers of SRAM.

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“…A literature survey [2] points out two main approaches to synthesize pass transistor circuits: one-transistor level synthesis based on decision diagrams and [3,4] second-library-based synthesis [5]. The first approach can be applicable to decide for minimum transistor configurations for various gate circuits, which can be suitably used as library for second approach.…”

Section: Introductionmentioning

confidence: 99%