A 16 nm FinFET circuit with triple function as digital multiplexer, active-high and active-low output decoder for high-performance SRAM architecture

To choose the option between an excess-1 result and a normal result,the conventional carry select adder (CCSA) employs two ripple-carry adders and amultiplexer in the last step. Second, whereas the proposed single-stage carry selectadder (SSCSA) avoids using full adders for the generation of both normal and excessresults, the present full adders require multiple full adders. A novel architecture isdeveloped and specifically designed to improve power dissipation and latency. It relieson a single circuit that produces normal/excess-1 results dependent on input carry.Heterogeneous logic combining CMOS, Dual Value Logic (DVAL), and TransmissionGate Logic (TRGL) with 22nm Fin-FETs powers the 1-bit SSCSA circuit. Bettercircuit regularity is displayed by the 4-bit SSCSA as it only uses one type of 1-bitSSCSA. With the use of Cadence Virtuoso, ADEL, and ADEXL at 22nm FinFETtechnology, all adders, including 4- and 8-bit adders, are designed, simulated, andexamined. According to the resulting study, the 4-bit SSCSA outperforms the bestadder currently in use in terms of speed performance and power dissipation by 17.6%and 27.6%, respectively. By comparison with all other designs, SSCSAs outperformthem at each and every corner.

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A 90 nm area and power efficient Carry Select Adder using 2–1 multiplexer based Excess-1 block

Battini

Bikshalu²,

Sivani³

2023

Eng. Res. Express

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This paper proposes a novel architecture of novel excess-1 adder basedCarry Select Adder (M2CSA) using single leaf cell i.e., 2-1 Multiplexer. The proposed4-, 8-, 16-, 32-, 64-bit M2CSAs use 2-1 Multiplexers only. The complex gates suchas XOR gates are completely eliminated which exist in existing Carry Select Adders(CaSeAs). A 64-bit M2CSA is distinctly decomposed for maintaining excellent cellregularity that uses one type of 2-1 Multiplexer cell. Ripple carry adder block inexisting designs are replaced with half adders by reducing the carry propagation tocertain extent. At the outset the speed of M2CSA is improved by overcoming carrypropagation through adder blocks, especially in 32- and 64-bit adders. The area isthe major concern for CaSeAs; is also reduced for M2CSAs by maintaining the cellregularity. The M2CSA and existing CaSeAs are designed using Verilog HDL. Thefunctional testing of all the designs is carried out using Cadence NCLaunch. All thedesigns are synthesized & implemented using Cadence Genus and Innovus respectivelyat 90nm technology node. The final ASIC layout of 64-bit M2CSA is more compact interms of area by an average of 17% compared to existing designs. The result analysisand comparison reveal that M2CSAs are better in terms of speed and power dissipationby 20% and 19% respectively. Therefore, M2CSA is best suitable to low-power, low area and high-speed applications

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A 16 nm FinFET circuit with triple function as digital multiplexer, active-high and active-low output decoder for high-performance SRAM architecture

Cited by 6 publications

References 35 publications

Design of efficient 22 nm, 20-FinFET full adder for low-power and high-speed arithmetic units

Design of efficient 22 nm, 20-FinFET full adder for low-power and high-speed arithmetic units

An efficient single-stage carry select adder using excess-1 FinFET circuit in 22 nm technology

A 90 nm area and power efficient Carry Select Adder using 2–1 multiplexer based Excess-1 block

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