Design of efficient 22 nm, 20-FinFET full adder for low-power and high-speed arithmetic units

Battini, Jeevan; Sivani, K.

doi:10.1007/s12633-022-02073-z

Cited by 4 publications

(2 citation statements)

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“…Carry propagation is the major concern in digital adders that are designed for high-speed applications. Once the carry propagation is mitigated at least to some extent then performance may be improved [1]. A well-known type of adder i.e., Carry Select Adder (CaSeA) is one of the fastest adders chosen for high-speed arithmetic applications.…”

Section: Introductionmentioning

confidence: 99%

“…This design replaces the second stage of CaSeA with a binary to excess-1 converter. Few previous works such as [1] and [3] focused on the design of efficient full adder which would be used in CaSeAs. The authors of [3] proposed a novel CNTFET-based full adder at 32nm CNFET technology for various parallel adders and their impact on large computing systems.…”

Section: Introductionmentioning

confidence: 99%

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A 90 nm area and power efficient Carry Select Adder using 2–1 multiplexer based Excess-1 block

Battini

Bikshalu²,

Sivani³

2023

Eng. Res. Express

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This paper proposes a novel architecture of novel excess-1 adder basedCarry Select Adder (M2CSA) using single leaf cell i.e., 2-1 Multiplexer. The proposed4-, 8-, 16-, 32-, 64-bit M2CSAs use 2-1 Multiplexers only. The complex gates suchas XOR gates are completely eliminated which exist in existing Carry Select Adders(CaSeAs). A 64-bit M2CSA is distinctly decomposed for maintaining excellent cellregularity that uses one type of 2-1 Multiplexer cell. Ripple carry adder block inexisting designs are replaced with half adders by reducing the carry propagation tocertain extent. At the outset the speed of M2CSA is improved by overcoming carrypropagation through adder blocks, especially in 32- and 64-bit adders. The area isthe major concern for CaSeAs; is also reduced for M2CSAs by maintaining the cellregularity. The M2CSA and existing CaSeAs are designed using Verilog HDL. Thefunctional testing of all the designs is carried out using Cadence NCLaunch. All thedesigns are synthesized & implemented using Cadence Genus and Innovus respectivelyat 90nm technology node. The final ASIC layout of 64-bit M2CSA is more compact interms of area by an average of 17% compared to existing designs. The result analysisand comparison reveal that M2CSAs are better in terms of speed and power dissipationby 20% and 19% respectively. Therefore, M2CSA is best suitable to low-power, low area and high-speed applications

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Section: Introductionmentioning

confidence: 99%