Design of a novel 1-bit full adder with hybrid logic for full-swing, area-efficiency, and high-speed

A Arul,; M Kathirvelu,

doi:10.1016/j.vlsi.2023.102123

Integration

2023

DOI: 10.1016/j.vlsi.2023.102123

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Design of a novel 1-bit full adder with hybrid logic for full-swing, area-efficiency, and high-speed

A Arul,

M Kathirvelu

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Design of a novel 1-bit full adder with hybrid logic for full-swing, area-efficiency, and high-speed

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References 18 publications

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