Technology mapping for high-performance static CMOS and pass transistor logic designs

Abstract

Two new techniques for mapping circuits are p r oposed in this paper. The rst method, called the odd-level transistor replacement OTR method, has a goal that is similar to that of technology mapping, but without the restriction of a xed library size, and maps a circuit to a virtual library of complex static CMOS gates. The second technique, the Static CMOS PTL method, uses a mix of static CMOS and pass transistor logic PTL to realize the circuit, and utilizes the relation between PTL and binary decision diagrams. The methods are very e cient and can handle all of the ISCAS'85 benchmark circuits in minutes. A c omparison of the results with traditional technology mapping using SIS on di erent libraries shows an average delay reduction above 18 for OTR, and an average delay reduction above 35 for the Static CMOS PTL method, with signi cant savings in the area. 1 Introduction Technology mapping is a cornerstone of the logic synthesis process and this area has been well studied in the past. Most existing techniques for technology mapping are based on static pre-characterized libraries, and can be classi ed into four categories: rule-based mapping 13 , graph matching 15 , direct mapping 18 and functional mapping 20. However, with changes in device technologies and the use of more complex static CMOS gates for example, in silicon-on-insulator technology, where longer transistor stacks are permitted, the limitations of the library-based design are becoming apparent. A library of xed size restricts the design choices that are available to a circuit designer, while a dynamic library that is generated on the y enables a better exploration of the This work is supported in part by a Lucent T echnologies DAC graduate scholarship, by a gift from Intel Corporation, and by the NSF under contracts MIP-9502556 and MIP-9796305. 1 design space. This paper develops techniques for generating complex gates on the y and performing technology mapping for two t ypes of technologies: Static CMOS: A topological mapping method called the odd-level transistor replacement OTR is developed for library-less mapping to complex static CMOS gates. Mixed static CMOS pass transistor logic PTL: A Boolean functional mapping method using binary decision diagrams BDD's to map logic to PTL is developed. This paper employs a similar dynamic programming based framework for both of these problems, and although they are solved as separate problems, we present them together in one publication for this reason. 1.1 Library-less mapping Traditional methods for technology mapping are directed towards a speci c library and are targeted towards objectives such as minimizing the circuit delay, minimizing the area and reducing the power dissipation. Using a pre-characterized library methodology has the inherent disadvantage that the quality of the results is dependent on the richness of the library: a library with a larger number of cells is likely to lead to better results than a sparsely populated library. The impact of the library size on logic synthesis was shown ...