Comprehensive study of 1-Bit full adder cells: review, performance comparison and scalability analysis

Abstract

Full Adder (FA) circuits are integral components in the design of Arithmetic Logic Units (ALUs) of modern computing systems. Recently, there have been massive research interests in this area due to the growing need for low-power and high-performance computing systems. Researchers have proposed a variety of FA cells with diverse design techniques, each having its pros and cons. As a result, a systematic method for performance comparison of FA cells using a common simulation platform has become necessary. In this work, we present an extensive study of FA cells. We have compared the performance of thirty-three (33) existing 1-bit FA cells. The drive powers of these FA cells have been compared by applying a variety of load conditions. In addition, the 1-bit FA cells have been extended to 32-bit structures to test their scalability and to investigate their performance in wide-word structures. We have determined that twenty-one (21) of the thirty-three (33) FA cells cannot operate in a 32-bit structure, even though some of them exhibit excellent performance as a 1-bit cell. The main finding of this research is that the single-bit performance parameters of FA cells should not be considered as the main basis for performance comparison. Any FA cell should be analyzed in a multi-bit structure to determine its practical effectiveness.

Quantum dynamics for energetic advantage in a charge-based classical full-adder

“…In summary, our estimates indicate that a coherent charge-based full adder in semiconductor quantum dots may have an energetic cost in the tens of meV range. This is an improvement by several orders of magnitude over the best estimates for the cost per bit operation in semiconductor transistor-based technologies, both in modern supercomputers [40] and other full-adder proposals [42]. In comparison with quantum dot cellular automata (QDCA), our estimated energetic cost is two to three orders of magnitude better than other estimates in this field.…”

“…Recent comprehensive reviews of semiconductor-based full-adders were done in Refs. [41,42] with detailed simulations of their power consumption, delay, and power-delay product (PDP), which quantifies the total energy spent during one gate operation. Overall, in the analysed proposals, the PDP ranges from 1.8 × 10 2 to 1.3 × 10 3 eV for one single-bit addition.…”

Quantum-Dot Cellular Automata-Based Full Adder Design: Comprehensive Review and Performance Comparison

“…Based on the design and performance parameters presented in Table 1, it can be observed that QCA FA in [69] has the lowest cell count (22). QCA FA in [81] utilized only 1 more cell than QCA FA in [64].…”

“…In binary addition, full adder (1-bit adder) is considered the basic unit cell [19,20]. Moreover, wide word length adders are mainly implemented based on a 1-bit FA cell [21,22]. In addition, diferent arithmetic functions need addition in their internal nodes.…”

A high‐performance full swing 1‐bit hybrid full adder cell

“…The Gate Diffusion Input (GDI) technique was another circuit design methodology by which logic circuits could be implemented with fewer transistors [15]. However, GDI logic faced the voltage degradation issue [16].…”