Synchronization combined PN code phase acquisition algorithm (SCA) for DSSS receiver

Huang, Chao-Wang; Wen, Kuei-Ann; Wu, Mau-Lin

doi:10.1109/mwscas.1999.867780

Cited by 2 publications

(2 citation statements)

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“…The threshold level of the comparator for the 11-bit Barker code is normally set to 7 or -7 where it can resist two chips of error [15]. When the cross-correlation value is greater than the threshold value, it is assumed that the alignment of the synchronizer is attained.…”

Section: Proposed Adder-less Digital Matched Filter Architecturementioning

confidence: 99%

“…When the cross-correlation value is greater than the threshold value, it is assumed that the alignment of the synchronizer is attained. The threshold level of the comparator for the 11-bit Barker code is normally set to 7 or -7 where it can resist two chips of error [15]. In the proposed matched filter, the chip error has been resisted to one chip.…”

Section: Proposed Adder-less Digital Matched Filter Architecturementioning

confidence: 99%

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Design of a novel adder‐less Barker matched filter for RFID

Amin

Reaz

Jalil

2013

Circuit Theory & Apps

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Radio frequency identification (RFID) is the utilization of the radio frequency for the purpose of identification. RFID is lagging behind due to vendor specific solutions and excessive implementation cost. A Wireless Fidelity (WiFi) compatible IEEE 802.11 RFID tag can overcome these limitations. IEEE 802.11 utilizes Direct Sequence Spread Spectrum (DSSS) technique and a matched filter is a vital block in a DSSS system. A low-power and low-area novel adder-less Barker matched filter is proposed in this paper by eliminating the conventional multiple multiplications. The matched filter designed in 0.18 mm CMOS technology achieves average and maximum power consumption of 33.747 mW and 8.08 mW, respectively and chip area of 0.41184 mm 2 only. The simulation result shows the correct matching of data against the threshold value. Compared with the conventional matched filter, the design achieves 25% power reduction (maximum power) and 51% chip area reduction. Therefore, the design will help to implement a low-power matched filter for IEEE 801.11 compatible RFID tag.

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Section: Proposed Adder-less Digital Matched Filter Architecturementioning

confidence: 99%

Section: Proposed Adder-less Digital Matched Filter Architecturementioning

confidence: 99%