2001
DOI: 10.1109/49.963801
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A programmable pipelined digital differential matched filter for DSSS receiver

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Cited by 6 publications
(3 citation statements)
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“…Comparing the summed result against a threshold value, the receiver achieves synchronization, and the information signal is detected and decoded [12]. By modifying the conventional architecture, Ching-Hung et al developed a programmablepipelined digital differential matched filter based on the Synchronization Combined PN code phase acquisition Algorithm (SCA) which utilized the 11-bit Barker code as shown in Figure 1 [8]. The SCA-based matched filter consists of pre-storage registers, multiple multipliers and adder circuits which also eventually cause high power consumption and increase the chip area.…”
Section: Conventional Matched Filtermentioning
confidence: 99%
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“…Comparing the summed result against a threshold value, the receiver achieves synchronization, and the information signal is detected and decoded [12]. By modifying the conventional architecture, Ching-Hung et al developed a programmablepipelined digital differential matched filter based on the Synchronization Combined PN code phase acquisition Algorithm (SCA) which utilized the 11-bit Barker code as shown in Figure 1 [8]. The SCA-based matched filter consists of pre-storage registers, multiple multipliers and adder circuits which also eventually cause high power consumption and increase the chip area.…”
Section: Conventional Matched Filtermentioning
confidence: 99%
“…Many algorithms and structures were proposed to reduce the power consumption and to increase the performance of the matched filters. To reduce the power consumption further, Chiou et al developed a programmable pipelined digital differential matched filter [8]. Differential coefficient schemes were first developed for low-power techniques based on the transposed-form structure [6].…”
Section: Introductionmentioning
confidence: 99%
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