SVX3: A deadtimeless readout chip for silicon strip detectors

Zimmerman, T.; Huffman, T. B.; Srage, J; Stroehmer, Raimund; Yarema, R.; Garcia-Sciveras, M; Luo, Linqing; Milgrome, O.

doi:10.1016/s0168-9002(97)01301-6

Cited by 26 publications

(6 citation statements)

References 5 publications

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“…As part of the Run IIa upgrade for D∅ the SVX2 and for CDF the SVX3 were designed to meet the needs of the experiments by a collaboration of engineers at Fermilab and Lawrence Berkeley Laboratory [4,5,6,7]. Requirements dictated that the devices should be capable of operating at an interaction rate as fast as 132 nsec, that it have optimal performance for detector capacitances between 10 and 35 pF, and that it have an analog pipeline with a maximum delay of about 4 µsec to allow time to form a trigger signal.…”

Section: Historical Developmentmentioning

confidence: 99%

SVX4 User's manual

Christofek¹,

Weber²,

Kreiger³

et al. 2005

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Section: Historical Developmentmentioning

confidence: 99%

SVX4 User's manual

Christofek¹,

Weber²,

Kreiger³

et al. 2005

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“…SVX4 keeps the same floorplan and low-impedance backside-grounding scheme that was proven successful for dead-timeless operation in SVX3D [3]. While the continuity of the floor plan expedited the layout somewhat, several major blocks required re-design for implementation in the 0.25 µm process.…”

Section: Design Conversionmentioning

confidence: 99%

“…The preamplifier stage has a programmable risetime, which limits the high-frequency noise. The pipeline operates as a ring of storage cells per channel, with the capability to remove up to 4 cells from the circular SVX4: A New Deep Submicron Readout IC for the Tevatron Collider at Fermilab B. Krieger 1 , S. Alfonsi 2,3 , N. Bacchetta 3 , S. Centro 2,3 , L. Christofek 4 , M. Garcia-Sciveres 1 , C. Haber 1 , K. Hanagaki 5 , J. Hoff 5 , M. Johnson 5 , H. von der Lippe 1 , E. Mandelli 1 , G. Meng 2,3 , A. Nomerotski 5 , D. Pellet 6 , P. Rapidis 5 , M. Utes 5 , J-P. Walder 1 , M. Weber 1 , W. Wester 5 , T. Wilkes 6 , R. Yarema 5 , W. Yao 6 , T. Zimmerman 5 S Fig. 1.…”

mentioning

confidence: 99%

SVX4: a new deep submicron readout IC for the Tevatron Collider at Fermilab

Krieger¹,

Alfonsi²,

Bacchetta³

et al. 2003

2003 IEEE Nuclear Science Symposium. Conference Record (IEEE Cat. No.03CH37515)

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SVX4 is the new silicon strip readout IC designed to meet the increased radiation tolerance requirements for Run IIb at the Tevatron collider. Devices have been fabricated, tested, and approved for production. The SVX4 design is a technology migration of the SVX3D design currently in use by CDF. Whereas SVX3D was fabricated in a 0.8 µ µ µ µm radiation-hard process, SVX4 was fabricated in a standard 0.25 µ µ µ µm mixed-signal CMOS technology using the "radiation tolerant by design" transistor topologies devised by the RD-49 collaboration. The specific cell layouts include digital cells developed by the ATLAS Pixel group, and full-custom analog blocks. Unlike its predecessors, the new design also includes the necessary features required for generic use by both the CDF and D0 experiments at Fermilab. Performance of the IC includes >20 MRad total dose tolerance, and ~2000 e-rms equivalent input noise charge with 40 pF input capacitance, when sampled at 132 ns period with an 80 ns preamp risetime. At the nominal digitize/readout rate of 106/53 MHz, the 9 mm x 6.3 mm die dissipates ~2 mW/channel average at 2.5 V. A review of typical operation, details of the design conversion process, and performance measurements are covered. I. INTRODUCTION VX4 is the new integrated circuit designed to meet the Run IIb upgrade requirements for the CDF and D0 experiments at the Fermilab Tevatron collider [1]. The 128channel ICs are wire-bonded directly to ac-coupled silicon strip detectors of varying capacitance in the range of 10-50 pF. The ICs themselves are mounted on two-chip (CDF and D0), fourchip (CDF), or ten-chip (D0) hybrid circuit boards, depending Manuscript received October 29, 2003.

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“…An analog memory [10] to capture all the peaks shown in Fig. 10 would need several hundred cells per channel and triggering would again be problematic.…”

Section: Multichannel Readout Systemmentioning

confidence: 99%

Analog peak detector and derandomizer for high-rate spectroscopy

Geronimo

Kandasamy

O’Connor

2002

IEEE Trans. Nucl. Sci.

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A compact and accurate readout system has been developed for high-rate spectroscopy with multi-element detectors. The fully self-triggered system multiplexes the signals from 32 detectors into a novel peak detector, which also serves as a derandomizer. The captured pulse heights are stored as analog samples before being presented to the ADC along with the corresponding channel addresses. The peak detector incorporates a new two-phase configuration that cancels offsets and other errors found in conventional designs. Offset cancellation gives the peak detector rail-to-rail sensing and driving capability and permits two or more peak detectors to be operated in parallel to serve as a data-driven analog memory. First experimental results on the new peak detector and derandomizer (PDD) circuit, fabricated in 0.35 m CMOS technology, include a 0.2% absolute accuracy for pulses with 500-ns peaking time, 2.7-V linear-input range, 3.5-mW power dissipation, 250-mV/s droop rate, and negligible dead time. We have tested the system with 32 CZT detectors and a 241 Am source. The spectra collected from the 32-channel system show that the noise performance of the preamp/shaper is not degraded by the multiplexing, peak detecting, and derandomizing operations.

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SVX3: A deadtimeless readout chip for silicon strip detectors

Cited by 26 publications

References 5 publications

SVX4 User's manual

SVX4 User's manual

SVX4: a new deep submicron readout IC for the Tevatron Collider at Fermilab

Analog peak detector and derandomizer for high-rate spectroscopy

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