SVX4 is the new silicon strip readout IC designed to meet the increased radiation tolerance requirements for Run IIb at the Tevatron collider. Devices have been fabricated, tested, and approved for production. The SVX4 design is a technology migration of the SVX3D design currently in use by CDF. Whereas SVX3D was fabricated in a 0.8 µ µ µ µm radiation-hard process, SVX4 was fabricated in a standard 0.25 µ µ µ µm mixed-signal CMOS technology using the "radiation tolerant by design" transistor topologies devised by the RD-49 collaboration. The specific cell layouts include digital cells developed by the ATLAS Pixel group, and full-custom analog blocks. Unlike its predecessors, the new design also includes the necessary features required for generic use by both the CDF and D0 experiments at Fermilab. Performance of the IC includes >20 MRad total dose tolerance, and ~2000 e-rms equivalent input noise charge with 40 pF input capacitance, when sampled at 132 ns period with an 80 ns preamp risetime. At the nominal digitize/readout rate of 106/53 MHz, the 9 mm x 6.3 mm die dissipates ~2 mW/channel average at 2.5 V. A review of typical operation, details of the design conversion process, and performance measurements are covered. I. INTRODUCTION VX4 is the new integrated circuit designed to meet the Run IIb upgrade requirements for the CDF and D0 experiments at the Fermilab Tevatron collider [1]. The 128channel ICs are wire-bonded directly to ac-coupled silicon strip detectors of varying capacitance in the range of 10-50 pF. The ICs themselves are mounted on two-chip (CDF and D0), fourchip (CDF), or ten-chip (D0) hybrid circuit boards, depending Manuscript received October 29, 2003.
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