SVX4: a new deep submicron readout IC for the Tevatron Collider at Fermilab

Abstract

SVX4 is the new silicon strip readout IC designed to meet the increased radiation tolerance requirements for Run IIb at the Tevatron collider. Devices have been fabricated, tested, and approved for production. The SVX4 design is a technology migration of the SVX3D design currently in use by CDF. Whereas SVX3D was fabricated in a 0.8 µ µ µ µm radiation-hard process, SVX4 was fabricated in a standard 0.25 µ µ µ µm mixed-signal CMOS technology using the "radiation tolerant by design" transistor topologies devised by the RD-49 collaboration. The specific cell layouts include digital cells developed by the ATLAS Pixel group, and full-custom analog blocks. Unlike its predecessors, the new design also includes the necessary features required for generic use by both the CDF and D0 experiments at Fermilab. Performance of the IC includes >20 MRad total dose tolerance, and ~2000 e-rms equivalent input noise charge with 40 pF input capacitance, when sampled at 132 ns period with an 80 ns preamp risetime. At the nominal digitize/readout rate of 106/53 MHz, the 9 mm x 6.3 mm die dissipates ~2 mW/channel average at 2.5 V. A review of typical operation, details of the design conversion process, and performance measurements are covered. I. INTRODUCTION VX4 is the new integrated circuit designed to meet the Run IIb upgrade requirements for the CDF and D0 experiments at the Fermilab Tevatron collider [1]. The 128channel ICs are wire-bonded directly to ac-coupled silicon strip detectors of varying capacitance in the range of 10-50 pF. The ICs themselves are mounted on two-chip (CDF and D0), fourchip (CDF), or ten-chip (D0) hybrid circuit boards, depending Manuscript received October 29, 2003.

A 12-bit multichannel ADC for pixel detectors in particle physics and nuclear imaging

“…The residual shows an INL less than ±1 LSB (0.024%). Compared with some reported measurement results [7,9,12], this chip achieved a comparable performance of linearity.…”

“…Although this scheme seems much more time-effective according to Table 1, the large area cost strictly prevents the integration with front end in a single chip. Besides, concerning detector channels M as many as 128 or even more [7], the mono-ADC will consequently turn the same time every round. As a result, the single-run time will increase to MT as a considerable amount, whereas the conversion time of the Wilkinson's scheme always remains the same with no impact of channels.…”

“…As shown in refs. [7][8][9], Wilkinson ADC has been widely used in various ASICs, making it an ideal start for ASIC study. As mentioned above, in order not to increase the complexity, SCA is not included in this first prototype but is ready to be included in the next generation.…”

Shielding and electrical performance of silicon detector supermodules

“…The bus cables carry three independent silicon strip modules each. A module is composed of two silicon sensors, glued and wirebonded together, and is read out by a beryllia hybrid carrying four SVX4 readout chips [6], [7]. The hybrid glued on top of the silicon sensors is electrically connected to the bus cable with wire bonds located in the 3 mm gaps between pairs of sensors.…”

CDF run IIb silicon vertex detector DAQ upgrade

“…Each module consists of two single-sided silicon sensors and one hybrid. Each hybrid has 4 SVX4 [12] chips for charge integration, digitization, and readout of silicon data. Each stave (six modules) comprises a single readout unit.…”