Successful Selective Epitaxial Si[sub 1−x]Ge[sub x] Deposition Process for HBT-BiCMOS and High Mobility Heterojunction pMOS Applications

Abstract

Si 1Ϫx Ge x /Si heterostructures are useful for numerous device applications where device performance is improved by band offsets and/or increased carrier mobility. The use of selective epitaxial growth for the implementation of Si 1Ϫx Ge x has some advantages compared to a nonselective growth process. However, some issues such as thickness nonuniformity ͑microloading on a micrometer scale and gas depletion on a wafer scale͒ and facet formation must be solved. In this paper, we give a detailed overview of our selective Si 1Ϫx Ge x growth process in a standard production-oriented chemical vapor deposition system for Ge contents between 0 and 32%. Our process allows layer deposition with no pattern dependence of the growth rate and Ge content ͑no microloading͒ and with a wafer scale layer nonuniformity that is better than the accuracy of the measurement techniques (ϳ2%). Facet formation was avoided by choosing the correct growth conditions and by preventing lateral growth over the mask material. Selective epitaxial layers did not show a degradation of photoluminescence characteristics. The layer quality is further demonstrated by the performance of Si 1Ϫx Ge x heterojunction bipolar transistors ͑0.35 and 0.25 m technology͒, and p-type Si 1Ϫx Ge x heterojunction metal oxide semiconductor devices ͑effective gate length down to 70 nm͒.

Selective epitaxial growth of boron- and phosphorus-doped Si and SiGe for raised sources and drains

“…Such a gas mixture enables to selectively grow Si or SiGe in the Si windows of dielectric-masked substrates [36], which is handy for the formation of either intrinsic or in situ doped elevated sources and drains.…”

“…Similarly, the Ge concentration increase (in between 26.3% and 27%, with a 26.6% mean value) when switching over from a blanket to the STI patterned wafer was found to be more modest than for the LOCOS one [36].…”

SiGe channel deposition by batch epitaxy

“…An in-situ etching of Si before SiGe deposition (recessed SiGe channel) as reported by Loo et al [10,11] avoids additional topography by SiGe channels for the PFET resulting in a clear benefit for the gate-first integration of high-k metal gate [12]. For the batch tool an in-situ etching process was developed achieving the same morphology to that of a single wafer tool with flat topography (Fig.…”

Control of topography and morphology for channel SiGe by in-situ HCl etching for future CMOS technologies with high-K metal gate

“…HCl etching at low HCl pressure has been widely studied [4,6,7] but it requires higher temperatures to obtain a reasonable etch rate. Etch tests at 850°C with low HCl partial pressure revealed a huge non-uniformity across the wafer indicating significant gas depletion ( Fig.…”