Subthreshold characteristics of insulated-gate field-effect transistors

Troutman, R.R.; Chakravarti, S. P.

doi:10.1109/tct.1973.1083759

Cited by 61 publications

(6 citation statements)

References 13 publications

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“…If the gate length is reduced more than 10-15 nm, it causes source-to-drain direct tunneling, resulting in the degradation of SCE. Previous research work already showed the limitations of the device scaling, and the Drain-Induced-Barrier-Lowering (DIBL) due to SCE [4][5][6][7][8][9][10][11]. As a result, multi-gate FinFETs were introduced to reduce the leakage current and improve the gate controllability of the transistor channel.…”

Section: Introductionmentioning

confidence: 99%

Electrical Characteristics of Bulk FinFET According to Spacer Length

et al. 2020

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This paper confirms that the electrical characteristics of FinFETs such as the on/off ratio, drain-induced barrier lowering (DIBL), and sub-threshold slope (SS) can be improved by optimizing the FinFET spacer structure. An operating voltage that can maintain a life of 10 years or more when hot-carrier injection is extracted. An excellent on/off ratio (7.73×107) and the best SS value were found at 64.29 mV/dec with a spacer length of 90 nm. Under hot carrier-injection conditions, the supply voltages that meet the 10-year lifetime condition are 1.11 V, 1.18 V, and 1.32 V for spacer lengths of 40 nm, 80 nm, and 120 nm, respectively. This experiment confirmed that, even at low drain voltages, the shorter is the spacer length, the greater is the deterioration. However, this increasing maximum operating voltage is very small when compared to the increase in the driving voltage required to achieve similar performance when the spacer length is increased; therefore, the effective life is expected to decrease. The results indicate that structural optimization must be performed to increase the driving current of the FinFET and prevent degradation of the analog performance.

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Section: Introductionmentioning

confidence: 99%

Electrical Characteristics of Bulk FinFET According to Spacer Length

et al. 2020

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“…Sub-threshold technology is a terminology that operating transistors in sub-threshold region by providing gate-to-source voltage lower than threshold voltage ( < ). The characteristic of transistor working in sub-threshold was studied since 1970s [24]. It is known that a minority channel is formed When is larger than , here calls superthreshold, or strong inversion.…”

Section: Implementation Of Sub-threshold Roicmentioning

confidence: 99%

Ultra-low power read-out integrated circuit design

Chen

Lee

Ren

2012

2012 IEEE National Aerospace and Electronics Conference (NAECON)

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“…Troutman and Chakravarti [2] have shown that diffusion dominates channel current in MOS transistors in weak inversion. The diffusion current injected by the source-to-substrate junction flows near the surface with a very long diffusion length and is collected by the drain.…”

Section: Measurements On Both N and P Devices Realizedmentioning

confidence: 99%

“…Introduction. -The known weak-inversion behaviour [1,2] of the MOS transistor assumes that the drain current is solely due to diffusion of the carriers. The related shot noise can be easily evaluated.…”

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confidence: 99%