Ultra-low power read-out integrated circuit design

Chen, Jian; Lee, G.; Ren, Shiyan

doi:10.1109/naecon.2012.6531045

Cited by 2 publications

(2 citation statements)

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“…Especially for the structure of the ROIC unit cell we proposed, four OPs are needed for an individual unit cell. To overcome the shortcoming, subthreshold technology is applied [4,5,13]. Subthreshold technology is operating transistors in subthreshold region by providing gate-to-source voltage lower than threshold voltage ( gs < th ).…”

Section: Design Of the Readout Unit Cellmentioning

confidence: 99%

“…Applications of FPAs with large format and high resolution put forward more harsh demands on the small layout area. In order to give an optimization for noise performance of a ROIC, a modularized noise analysis method is proposed for a readout cell, consisting of an integrator and a new type of correlated double sampler (CDS), both of which are switched capacitor circuits, where all the MOSFETs are optimized in subthreshold region to be acceptable to the power limitation of large format FPAs [4,5]. The modularized noise analysis begins with the architecture of the readout cell that is for pixel level ROICs, operating in snapshot mode.…”

Section: Introductionmentioning

confidence: 99%

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A Modularized Noise Analysis Method with Its Application in Readout Circuit Design

Wang

Shi

2015

VLSI Design

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A readout integrated circuit (ROIC) is a crucial part that determines the quality of imaging. In order to analyze the noise of a ROIC with distinct illustration of each noise source transferring, a modularized noise analysis method is proposed whose application is applied for a ROIC cell, where all the MOSFETs are optimized in subthreshold region, leading to the power dissipation 2.8 μW. The modularized noise analysis begins with the noise model built using transfer functions and afterwards presents the transfer process of noise in the form of matrix, through which we can describe the contribution of each noise source to the whole output noise clearly, besides optimizing the values of key components. The optimal noise performance is obtained under the limitation of layout area less than 30 μm × 30 μm, resulting in that the integration capacitor should be selected as 0.74 pF to achieve an optimal noise performance, the whole output noise reaching the minimum value at 74.1 μV. In the end transient simulations utilizing Verilog-A are carried out for comparisons. The results showing good agreement verify the feasibility of the method presented through matrix.

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Section: Design Of the Readout Unit Cellmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%