Electrical Characteristics of Bulk FinFET According to Spacer Length

Abstract

This paper confirms that the electrical characteristics of FinFETs such as the on/off ratio, drain-induced barrier lowering (DIBL), and sub-threshold slope (SS) can be improved by optimizing the FinFET spacer structure. An operating voltage that can maintain a life of 10 years or more when hot-carrier injection is extracted. An excellent on/off ratio (7.73×107) and the best SS value were found at 64.29 mV/dec with a spacer length of 90 nm. Under hot carrier-injection conditions, the supply voltages that meet the 10-year lifetime condition are 1.11 V, 1.18 V, and 1.32 V for spacer lengths of 40 nm, 80 nm, and 120 nm, respectively. This experiment confirmed that, even at low drain voltages, the shorter is the spacer length, the greater is the deterioration. However, this increasing maximum operating voltage is very small when compared to the increase in the driving voltage required to achieve similar performance when the spacer length is increased; therefore, the effective life is expected to decrease. The results indicate that structural optimization must be performed to increase the driving current of the FinFET and prevent degradation of the analog performance.

Device and Circuit Analysis of Double Gate Field Effect Transistor with Mono-Layer WS2-Channel at Sub-2 nm Technology Node

“…However, although the ION/IOFF ratio and subthreshold swing (SS) are noticeably changed in silicon FinFET, there is little Region (R EXT ) increases. This phenomenon is the same as the general phenomenon that appears in devices such as silicon FinFET [21]. However, although the I ON /I OFF ratio and subthreshold swing (SS) are noticeably changed in silicon FinFET, there is little I ON /I OFF ratio and SS change because the L SPC change is very small in this work (in all cases of L SPC = 8 nm ~9.5 nm of DG WS 2 -FET, the I ON /I OFF ratio is about 1.33 × 10 5 , and SS is about 69 mV/dec).…”

“…Figure 3b,c Region (REXT) increases. This phenomenon is the same as the general phenomenon that appears in devices such as silicon FinFET [21]. However, although the ION/IOFF ratio and subthreshold swing (SS) are noticeably changed in silicon FinFET, there is little Region (R EXT ) increases.…”

Effects of Varying the Fin Width, Fin Height, Gate Dielectric Material, and Gate Length on the DC and RF Performance of a 14-nm SOI FinFET Structure

“…The variation of the threshold voltage, subthreshold slope, and I on /I off ratio at two gate lengths with different fin widths is shown in Figures 20-22, respectively. As can be observed, V th and SS are sensitive to W fin for a small gate length due to the short channel effect as illustrated in Figures 20 and 21, respectively [22][23][24][25][26][27]. As shown in Figure 22, the highest value of I on /I off occurs at the lowest fin width.…”

“…TiO 2 is used as gate dielectric material to replace HfO 2 for better controllability of the gate over the channel. As it is well-known, the electrostatic integrity can be improved by reducing the thickness of the gate oxide [26]. The high-k dielectric thickness is chosen to be 2 nm.…”

Design and Analysis of InP/InAs/AlGaAs Based Cylindrical Surrounding Double-Gate (CSDG) MOSFETs With La2O3 for 5-nm Technology

“…The high ION current is accomplished by tunneling in the gate region rather than the gate width specified; however, the value of IOFF is low, and it mainly depends on spacer thickness. The investigations that the spacer length thickness in any compound semiconductor technology must be within the optimal limit had been done [40][41][42][43][44][45]. Exceeding the limit leads to an increase in source and drain resistances and causes an overall degradation by a decrease in on-state current ION.…”