Currently 2D crystals are being studied intensively for use in future nano-electronics, as conventional semiconductor devices face challenges in high power consumption and short channel effects when scaled to the quantum limit. Toward this end, achieving barrier-free contact to 2D semiconductors has emerged as a major roadblock. In conventional contacts to bulk metals, the 2D semiconductor Fermi levels become pinned inside the bandgap, deviating from the ideal Schottky-Mott rule and resulting in significant suppression of carrier transport in the device. Here we realized MoS 2 polarity control without extrinsic doping by employing 1D elemental metal contact scheme. Use of high work function palladium (Pd) or gold (Au) achieved high quality p-type dominant contact to intrinsic MoS 2 , realizing Fermi level de-pinning. Field-effect transistors (FET) with Pd edge contact and Au edge contact show high performance with the highest hole mobility reaching 330 cm 2 /Vs and 432 cm 2 /Vs at 300 K respectively. The ideal Fermi level alignment allows creation of p-and n-type FETs on the same intrinsic MoS 2 flake using Pd and low work function molybdenum (Mo) contacts, respectively. This device acts as an efficient inverter, a basic building block for semiconductor integrated circuits, with gain reaching 15 at V D =5 V.

A gate-controlled metal-semiconductor barrier modulation and its effect on carrier transport were investigated in two-dimensional (2D) transition metal dichalcogenide (TMDC) field effect transistors (FETs). A strong photoresponse was observed in both unipolar MoS2 and ambipolar WSe2 FETs (i) at the high drain voltage due to a high electric field along the channel for separating photo-excited charge carriers and (ii) at the certain gate voltage due to the optimized barriers for the collection of photo-excited charge carriers at metal contacts. The effective barrier height between Ti/Au and TMDCs was estimated by a low temperature measurement. An ohmic contact behavior and drain-induced barrier lowering (DIBL) were clearly observed in MoS2 FET. In contrast, a Schottky-to-ohmic contact transition was observed in WSe2 FET as the gate voltage increases, due to the change of majority carrier transport from holes to electrons. The gate-dependent barrier modulation effectively controls the carrier transport, demonstrating its great potential in 2D TMDCs for electronic and optoelectronic applications.

We report a novel cleaning technique for few-layer graphene (FLG) by using inductively coupled plasma (ICP) of Ar with an extremely low plasma density of 3.5 × 10(8) cm(-3). It is known that conventional capacitively coupled plasma (CCP) treatments destroy the planar symmetry of FLG, giving rise to the generation of defects. However, ICP treatment with extremely low plasma density is able to remove polymer resist residues from FLG within 3 min at a room temperature of 300 K while retaining the carbon sp(2)-bonding of FLG. It is found that the carrier mobility and charge neutrality point of FLG are restored to their pristine defect-free state after the ICP treatment. Considering the application of graphene to silicon-based electronic devices, such a cleaning method can replace thermal vacuum annealing, electrical current annealing, and wet-chemical treatment due to its advantages of being a low-temperature, large-area, high-throughput, and Si-compatible process.