Device and Circuit Analysis of Double Gate Field Effect Transistor with Mono-Layer WS2-Channel at Sub-2 nm Technology Node

Abstract

In this work, WS2 was adopted as a channel material among transition metal dichalcogenides (TMD) materials that have recently been in the spotlight, and the circuit power performance (power consumption, operating frequency) of the monolayer WS2 field-effect transistor with a double gate structure (DG WS2-FET) was analyzed. It was confirmed that the effective capacitance, which is circuit power performance, was greatly changed by the extrinsic capacitance components of DG WS2-FET, and the spacer region length (LSPC) and dielectric constant (KSPC) values of the spacer that could affect the extrinsic capacitance components were analyzed to identify the circuit power performance. As a result, when LSPC is increased by 1.5 nm with the typical spacer material (KSPC = 7.5), increased operating speed (+4.9%) and reduced active power (–6.8%) are expected. In addition, it is expected that the spacer material improvement by developing the low-k spacer from KSPC = 7.5 to KSPC = 2 at typical LSPC = 8 nm can increase the operating speed by 36.8% while maintaining similar active power consumption. Considering back-end-of-line (BEOL), the change in circuit power performance according to wire length was also analyzed. From these results, it can be seen that reducing the capacitance components of the extrinsic region is very important for improving the circuit power performance of the DG WS2-FET.

Investigation of Optimal Architecture of MoS2 Channel Field-Effect Transistors on a Sub-2 nm Process Node

“…29−31 In a previous study, a double-gate (DG) structured FET with WS 2 , a type of TMDC material, as a channel was analyzed by segmenting resistance and capacitance, which are elements that affect logic circuit performance, and the capacitance of the spacer region, which had the greatest effect, was presented. 32 In this work, we analyzed which FET structure is optimal among single-gate 2D FETs and multigate 3D FETs according to the MoS 2 channel thickness (number of layers), which was not considered in previous studies. To this end, the circuitlevel speed and power consumption characteristics including the parasitic RC component were analyzed in the sub-2 nm process node using the atomic-level simulation results that confirmed the electrical characteristics of the MoS 2 material by thickness in the previous work.…”

“…In a previous study, a double-gate (DG) structured FET with WS 2 , a type of TMDC material, as a channel was analyzed by segmenting resistance and capacitance, which are elements that affect logic circuit performance, and the capacitance of the spacer region, which had the greatest effect, was presented . In this work, we analyzed which FET structure is optimal among single-gate 2D FETs and multigate 3D FETs according to the MoS 2 channel thickness (number of layers), which was not considered in previous studies.…”

Nanotechnology for Electronic Materials and Devices

“…(iii) Other paper focus on advanced nanoscale characterization, mainly based on scanningprobe methods (scanning non linear dielectric microscopy [12] and high-resolution scanning capacitance spectroscopy [13]), as well as on surface optical techniques (photoluminescence and spectroscopic ellipsometry) [14]. (iv) Finally, some papers are dedicated to device performances [15] and circuit analysis [16], providing evidence that it is crucial to move from research to technological development to control the quality of innovative products and functionalities.…”