Substrate crosstalk suppression capability of silicon-on-insulator substrates with buried ground planes (GPSOI)

Hamel, J.S.; Stefanou, S.; Bain, Michael; Armstrong, B.M.; Gamble, Harold

doi:10.1109/75.846923

Cited by 27 publications

(12 citation statements)

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“…Using these values it was possible to calculate the silicon doping level from the minimum series capacitance to be 1. 3 cm , consistent with the starting active wafer resistivity.…”

Section: Substrate Characterizationsupporting

confidence: 78%

“…Wafer bonding technology was used in the production of these SOI substrates. This technology together with the crosstalk measurement techniques and results have been reported previously over the frequency range 0.5-50 GHz [3]- [5]. The results show a 20-dB superior performance to any other crosstalk suppression strategy.…”

Section: Introductionmentioning

confidence: 50%

“…The effective buried insulator is therefore a composite layer consisting in this case of a thermal oxide 100 nm thick and the polysilicon layer 100 nm thick. Substrates of this type have been used in the GPSOI crosstalk characterization [3]- [5].…”

Section: Gpsoi Substratementioning

confidence: 99%

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Electrical characterization of SOI substrates incorporating WSi/sub x/ ground planes

Bain

Jin

Loh

et al. 2005

IEEE Electron Device Lett.

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Silicon-on-insulator (SOI) substrates incorporating tungsten silicide ground planes (GPs) have been shown to offer the lowest reported crosstalk figure of merit for application in mixed signal integrated circuits. The inclusion of the silicide layer in the structure may lead to stress or defects in the overlying SOI layers and resultant degradation of device performance. It is therefore essential to establish the quality of the silicon on the GPSOI substrate. MOS capacitor structures have been employed in this paper to characterize these GPSOI substrates for the first time. High quality MOS capacitor characteristics have been achieved with minority carrier lifetime of 0 8 ms. These results show that the substrate is suitable for device manufacture with no degradation in the silicon due to stress or metallic contamination resulting from the inclusion of the underlying silicide layer.

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“…Using these values it was possible to calculate the silicon doping level from the minimum series capacitance to be 1. 3 cm , consistent with the starting active wafer resistivity.…”

Section: Substrate Characterizationsupporting

confidence: 78%

Section: Introductionmentioning

confidence: 50%

See 1 more Smart Citation

Electrical characterization of SOI substrates incorporating WSi/sub x/ ground planes

Bain

Jin

Loh

et al. 2005

IEEE Electron Device Lett.

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“…This approach reduces parasitic capacitances, leakage currents and the devices size. Furthermore, the SOI substrate eliminates parasitic substrate transistors and latchup and has the ability to reduce crosstalk, particularly when combined with buried groundplanes [20], [21]. These benefits make SiGe HBTs on SOI attractive for mixed-signal RF applications.…”

mentioning

confidence: 99%

“…1 shows the concept of the silicide SOI (SSOI) SiGe HBT technology. Key features of the technology are the inclusion of a buried silicide layer above the buried oxide layer for reduction of collector resistance and a buried silicide groundplane below the buried oxide layer for crosstalk suppression [20]. The n+ buried layer is needed in the SSOI process to prevent the formation of a Schottky contact between the buried silicide and the silicon collector.…”

mentioning

confidence: 99%

SiGe HBTs on Bonded SOI Incorporating Buried Silicide Layers

Bain

Mubarek

Bonar

et al. 2005

IEEE Trans. Electron Devices

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Abstract-A technology is described for fabricating SiGe heterojunction bipolar transistors (HBTs) on wafer-bonded silicon-oninsulator (SOI) substrates that incorporate buried tungsten silicide layers for collector resistance reduction or buried groundplanes for crosstalk suppression. The physical structure of the devices is characterized using cross section transmission electron microscopy, and the electrical properties of the buried tungsten silicide layer are characterized using sheet resistance measurements as a function of bond temperature.

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