SiGe HBTs on Bonded SOI Incorporating Buried Silicide Layers

Abstract

Abstract-A technology is described for fabricating SiGe heterojunction bipolar transistors (HBTs) on wafer-bonded silicon-oninsulator (SOI) substrates that incorporate buried tungsten silicide layers for collector resistance reduction or buried groundplanes for crosstalk suppression. The physical structure of the devices is characterized using cross section transmission electron microscopy, and the electrical properties of the buried tungsten silicide layer are characterized using sheet resistance measurements as a function of bond temperature.

Silicon quantum cascade lasers for THz sources

“…buried silicide layers. These buried silicide layers are formed by a bond and etch-back technique and have sufficiently high conductivities to behave as buried metallic reflectors [6]. In this paper we will present evidence of high quality quantum cascade active regions on top of buried tungsten silicide layers and electroluminescence from these structures.…”

Toward Silicon-Based Lasers for Terahertz Sources

“…The silicide layer has the advantage of having a much higher electrical conductivity than a semiconductor, and typically within one order of magnitude of good metals. A full description of the fabrication of a buried silicide layer can be found elsewhere [24]. The four most mature silicide technologies are WSi 2 , CoSi 2 , TiSi 2 , and NiSi.…”

“…Fig. 11 shows a TEM of a wafer we have grown with a buried WSi 2 layer wafer [24] to produce high modal overlap. It consists of 4.005 µm of SiGe quantum cascade active region, preceded by a 0.990-µm-thick Si 0.8 Ge 0.2 constant composition layer, a 2.830-µm graded Si x Ge 1−x buffer, and a 1.280-µm-thick Si layer, on top of a 440-nm-thick WSi 2 layer.…”

Epilayer Optimization of NPN SiGe HBT with n+ Buried Layer Compatible With Fully Depleted SOI CMOS Technology

“…Recently, simulation study of SOI HBT with buried layer has been performed [18] and a high performance SOI HBT compatible with 130 nm SOI CMOS technology is proposed. Though SiGe HBT with buried silicide layer has been discussed in [19], the HBT is not compatible with advanced fully depleted SOI CMOS technology. A fully self aligned Si/SiGeC HBT with boron in-situ doped polybase, phosphorus doped emitter and nickel silicide has been reported in [20].…”

“…Using different device design approach researchers have explored performance improvement in HBT [18][19][20][21].…”