Study of void formation kinetics in Cu interconnects using local sense structures

Croes, Kristof; Lofrano, Melina; Wilson, Christopher J.; Carbonell, L.; Siew, Yong Kong; Beyer, Gerald; Tőkei, Zs.

doi:10.1109/irps.2011.5784495

Cited by 13 publications

(2 citation statements)

References 15 publications

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“…Such barrier is representative for extremely thin conductive barriers. The void formation model has been taken from [10][11]: the void is assumed to form with a fixed length (assumed to be 50nm in our calculations) into the line with a height H void as a function of time. The assumptions of barrier thickness and resistivity for the different cases are summarized in table I.…”

Section: Resultsmentioning

confidence: 99%

Constant voltage electromigration for advanced BEOL copper interconnects

Tang

Croes

Jourdan

et al. 2015

2015 IEEE International Reliability Physics Symposium

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For characterizing the electromigration (EM) reliability of advanced interconnects, we propose a constant voltage approach (CV-EM) as an alternative method to traditional constant current tests (CI-EM). As extremely scaled interconnects require very thin barriers, their current shunting capabilities will be reduced. When close to full void formation, we show that this lack of current shunting capability leads to unrealistically high stress conditions during CI-EM while more realistic stresses are induced during CV-EM. We also demonstrate that the void detection capability is highly improved after CV-EM. We use simulations and experiments to compare CV-EM with CI-EM where we obtain a) slightly longer lifetimes for CV-EM, b) the same failure mechanisms and c) similar E a and n values.

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Section: Resultsmentioning

confidence: 99%

Constant voltage electromigration for advanced BEOL copper interconnects

Tang

Croes

Jourdan

et al. 2015

2015 IEEE International Reliability Physics Symposium

Self Cite

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“…2) Growth phase: The resistance of the line does not change significantly even after void nucleation. The void grows and reaches a critical size to cover the cross-section of the line, after which the resistance of the line starts to increase [22]. The time required for the void to grow to a critical size ( l crit ) after σ crit is reached is called the incubation time (t i ).…”

Section: Proposed Em Analysis Model a Em Model Calibrationmentioning

confidence: 99%

Workload-Aware Electromigration Analysis in Emerging Spintronic Memory Arrays

Nair

Mayahinia

Tahoori

et al. 2021

IEEE Trans. Device Mater. Relib.

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Electromigration (EM) has emerged as a major reliability concern for interconnects in advanced technology nodes. Most of the existing EM analysis works focus on the power lines. There exists a limited amount of work which analyzes EM failures in the signal lines. However, various emerging spintronicbased memory technologies such as the Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM) and the Spin Orbit Torque Magnetic Random Access Memory (SOT-MRAM) have high current densities as compared to the conventional Static Random Access Memory (SRAM). These high current densities can lead to EM failures in the signal lines such as bit-line (BL) of these memories. Furthermore, these signal lines have workloaddependent stress as opposed to the conventional DC stress of power distribution networks. In this work, we model the EM failures in the BL of a typical STT memory array with realistic workloads. The analysis is based on physics-based EM model, which is calibrated based on industrial measurement data. The results show that the current densities in the STT arrays can be large enough to cause EM failures in the signal lines with running realistic workloads and that these failures are highly workload-dependent.

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Airgaps in nano-interconnects: Mechanics and impact on electromigration

Zahedmanesh

Besser

Wilson

et al. 2016

Journal of Applied Physics

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In this study, electromigration (EM) of interconnects (90 nm pitch) with airgaps was investigated using a combination of computational mechanics, analytical modelling, and EM experiments. EM experiments reveal that airgapped Cu lines without dielectric liner (non-capsulated) fail early by voiding in the EM tests due to oxidation and deterioration of interfacial adhesion at Cu interfaces. Also at high temperature regimes, extrusive failures under thermal compressive stresses were observed in airgapped Cu lines without dielectric liner. Therefore, Cu encapsulation using a conformal dielectric liner of adequate thickness is necessary in order to ensure hermeticity and provide endurance to the thermal and EM induced extrusive stresses. For an airgapped interconnect with a hermetic 5 nm PECVD conformal carbon doped silicon nitride (SiCN) liner deposited at 370 °C, a (jL)crit comparable to that of non-airgapped interconnects (with ultra-low-k dielectric 2.5 inter-layer dielectric) was predicted by the simulations. The process-oriented simulations reveal, however, that the tensile stress in Cu lines increases linearly with the thickness of the SiCN liner. Therefore, increasing the thickness of the dielectric liner beyond the minimum thickness required for hermeticity was found to impact the critical line length (jL)crit adversely.

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Study of void formation kinetics in Cu interconnects using local sense structures

Cited by 13 publications

References 15 publications

Constant voltage electromigration for advanced BEOL copper interconnects

Constant voltage electromigration for advanced BEOL copper interconnects

Workload-Aware Electromigration Analysis in Emerging Spintronic Memory Arrays

Airgaps in nano-interconnects: Mechanics and impact on electromigration

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