Study of the stability of polycrystalline silicon by means of the behavior of thin film transistors under gate bias stress

Low temperature amorphous and nanocrystalline silicon thin film transistors deposited by Hot-Wire CVD on glass substrate

“…The small V T shift observed in this case (∆V T ~ 0.5 V), imputable to the disordered structure of nc-Si:H [8], is another argument to use these TFTs in the OLED addressing.…”

Performance and stability of low temperature hydrogenated amorphous silicon thin film transistors fabricated on stainless steel substrate

“…The stress condition is the same as the BTS. The straight lines lead to the stretched exponential form for the normalized threshold shift, which can be written as [13] a-Si:H TFT stability in terms of V TH shift can be explained by high and low field bias stresses, meaning that metastable states in the a-Si:H at low positive bias are created, while charge trapping in SiN X at high positive and negative bias has occurred. Thus, it can not be expected good stability in high field bias case due to the effect of low power SiN X .…”