Study of sub-5 nm RRAM, tunneling selector and selector less device

Abstract

By using sidewall electrode technology, both record small functional TiO 2 selection device (1 × 5 nm 2 ) and HfO 2 based RRAM device (1 × 3 nm 2 ) were for the first time successfully demonstrated in this work, improving the understanding of the switching mechanism in an ultra-small, functional resistive random access memory (RRAM) device. The tunneling based low temperature back-end selection devices show high driving current density of > 10 MA/cm 2 and selectivity of > 10 3 . The pulse driven cycle endurance of sub-5nm selection device and RRAM device reaches 10 6 and 10 3 , respectively. Well controlled TiO 2 barrier produced with conformal plasma oxidation exhibits tight uniformity. The 1 × 3 nm 2 RRAM device exhibited an excellent performance, featuring a large on/off verified window (>100), and reasonable reliability (stress time > 10 3 s). Furthermore, the 1 × 3 nm 2 RRAM device exhibited distinctive unipolar behavior when a high voltage and rapid switching operation (7 V, 50 ns) were applied. We also study on double oxide layer device and propose a physical mechanism picture to compare with previous study. This technology demonstrates the potential of future atomicscale memories.

Modeling of RRAM With Embedded Tunneling Barrier and Its Application in Logic in Memory

“…Simulated I-V characteristics of RRAM with tunneling barrier (TB) under quasi-DC condition with ramp rate at 1V/s. The red dots are extracted from the 3nm device of [7]. The green line is the simulated result without TB based on our previous study [17].…”

“…memory elements [6]. Selector devices for high density applications, relying on tunneling mechanism, can meet the aforementioned requirements, as reported in [7].…”

Advances of embedded resistive random access memory in industrial manufacturing and its potential applications

“…The sub-5 nm selective device and RRAM device exhibited pulse-driven cycles reaching 10 6 and 10 3 , respectively, with the TiO 2 barrier layer showing good uniformity. This work showcased the favorable performance of embedded RRAM for development at low process nodes [127]. For multilayer RRAM devices, Yu et al explored the scalability of a 2-layer RRAM crossbar array architecture for 10 nm nodes.…”

Recent Progress in Selector and Self‐Rectifying Devices for Resistive Random‐Access Memory Application

“…Their work helps us understand the switching mechanism of RRAM devices. [156] In the case of nonfilamentary RS devices, the tunneling barrier helps gain interesting memory properties.…”