2020
DOI: 10.1109/jeds.2020.3008172
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Modeling of RRAM With Embedded Tunneling Barrier and Its Application in Logic in Memory

Abstract: This paper proposes a modeling technique for the evaluation of RRAM with embedded tunneling barrier that serves as an embedded selector, enabling high density integration while reducing the leakage current in a memory array. The further exploration of various biasing and pulsing schemes is provided so as to optimize programming efficiency for logic-in-memory application.

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Cited by 2 publications
(1 citation statement)
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“…It could quickly form a conductive path that leads to LRS Ohmic current and reduces the tunneling gap distance. The time and the thermal-related positive feedback behavior are expressed as [12] 𝑑𝑔 𝑑𝑡 = 𝑣 0 𝑒𝑥𝑝 (…”
Section: B Gap Formationmentioning
confidence: 99%
“…It could quickly form a conductive path that leads to LRS Ohmic current and reduces the tunneling gap distance. The time and the thermal-related positive feedback behavior are expressed as [12] 𝑑𝑔 𝑑𝑡 = 𝑣 0 𝑒𝑥𝑝 (…”
Section: B Gap Formationmentioning
confidence: 99%