Stress-induced voiding in aluminum and copper interconnects

Hommel, M.; Fischer, A.; Glasow, A. von; Zitzelsberger, A.E.

doi:10.1063/1.1469900

Cited by 13 publications

(7 citation statements)

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“…We validate equation ( 9) by comparing the calculated SIV lifetime with experimental values taken from [38]. In the work [38], since the SIV failure extended throughout the line width, equation (9a) is employed for the calculation.…”

Section: Siv Lifetime Modelingmentioning

confidence: 98%

Stress-induced voiding study in integrated circuit interconnects

Hou¹,

Tan²

2008

Semicond. Sci. Technol.

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An analytical equation for an ultralarge-scale integration interconnect lifetime due to stress-induced voiding (SIV) is derived from the energy perspective. It is shown that the SIV lifetime is strongly dependent on the passivation quality at the cap layer/interconnect interface, the confinement effect by the surrounding materials to the interconnects, and the available diffusion paths in the interconnects. Contrary to the traditional power-law creep model, we find that the temperature exponent in SIV lifetime formulation is determined by the available diffusion paths for the interconnect atoms and the interconnect geometries. The critical temperature for the SIV is found to be independent of passivation integrity and dielectric confinement effect. Actual stress-free temperature (SFT) during the SIV process is also found to be different from the dielectric/cap layer deposition temperature or the final annealing temperature of the metallization, and it can be evaluated analytically once the activation energy, temperature exponent and critical temperature are determined experimentally. The smaller actual SFT indicates that a strong stress relaxation occurs before the high temperature storage test. Our results show that our SIV lifetime model can be used to predict the SIV lifetime in nano-interconnects.

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Section: Siv Lifetime Modelingmentioning

confidence: 98%

Stress-induced voiding study in integrated circuit interconnects

Hou¹,

Tan²

2008

Semicond. Sci. Technol.

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“…Primarily, prior works (Oh et al 2013;Heryanto et al 2011;Weide-zaage 2012;Wu et al 2010;O Brien 2013;Hommel et al 2002;Paik et al 2004) have considered crystalline copper and isotropic material properties for reliability simulations. A clear dependance between the copper microstructure in nanoscale interconnects, void formation kinetics, and electromigration statistics has been established through experiments (Cao et al 2013).…”

Section: Introductionmentioning

confidence: 99%

Modeling the copper microstructure and elastic anisotropy and studying its impact on reliability in nanoscale interconnects

Basavalingappa

Shen

Lloyd

2017

Mech Adv Mater Mod Process

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Background: Copper is the primary metal used in integrated circuit manufacturing of today. Even though copper is face centered cubic it has significant mechanical anisotropy depending on the crystallographic orientations. Copper metal lines in integrated circuits are polycrystalline and typically have lognormal grain size distribution. The polycrystalline microstructure is known to impact the reliability and must be considered in modeling for better understanding of the failure mechanisms. Methods: In this work, we used Voronoi tessellation to model the polycrystalline microstructure with lognormal grainsize distribution for the copper metal lines in test structures. Each of the grains is then assigned an orientation with distinct probabilistic texture and corresponding anisotropic elastic constants based on the assigned orientation. The test structure is then subjected to a thermal stress.

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“…For SIV, there exists a critical temperature at which the SIV lifetime is the minimum. This is anticipated since there are two main processes which determine the SIV failure rate [12], namely the driving force by stress gradient and the atomic diffusion. Such a critical temperature is also observed in figure 2, where the median resistance change at 200 • C is higher than that at 150 • C and 250 • C. Therefore, the critical temperature is around 200 • C, close to 190 • C as reported by Ogawa et al [17] for Cu line-via structures.…”

Section: Resultsmentioning

confidence: 99%

“…While stress-induced voiding in line structures has been studied extensively [6,[8][9][10], the void formation and evolution behavior of SIV in line-via structures are still not well understood [11] despite the presence of SIV void in via as observed experimentally [11][12][13]. This may be due to the complex geometry of line-via structures as compared to its line structure counterpart.…”

Section: Introductionmentioning

confidence: 99%

Comparison of stress-induced voiding phenomena in copper line–via structures with different dielectric materials

Hou¹,

Tan

2009

Semicond. Sci. Technol.

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The package level stress-induced voiding (SIV) test of Cu dual-damascene line-via structures is performed. Two different dielectrics, undoped silica glass (USG) and carbon doped oxide (CDO), are used in this work. After 1344 h of high temperature storage test, the resistance drift of USG interconnects is found to be much smaller than that of CDO interconnects and voids are located at the bottom of the via for both USG and CDO interconnects. However, horizontal voids grown along the via bottom is observed for USG interconnects, whilst voids are found to grow vertically along the via sidewall for CDO interconnects. The phenomena are explained using finite element analysis in this work, and the observed poor SIV performance for CDO interconnects is also explained. With this finite element analysis, the implications of different low-k dielectrics on SIV reliability are discussed.

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Stress-induced voiding in aluminum and copper interconnects

Cited by 13 publications

References 0 publications

Stress-induced voiding study in integrated circuit interconnects

Stress-induced voiding study in integrated circuit interconnects

Modeling the copper microstructure and elastic anisotropy and studying its impact on reliability in nanoscale interconnects

Comparison of stress-induced voiding phenomena in copper line–via structures with different dielectric materials

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