Stress-induced voiding study in integrated circuit interconnects

Abstract

An analytical equation for an ultralarge-scale integration interconnect lifetime due to stress-induced voiding (SIV) is derived from the energy perspective. It is shown that the SIV lifetime is strongly dependent on the passivation quality at the cap layer/interconnect interface, the confinement effect by the surrounding materials to the interconnects, and the available diffusion paths in the interconnects. Contrary to the traditional power-law creep model, we find that the temperature exponent in SIV lifetime formulation is determined by the available diffusion paths for the interconnect atoms and the interconnect geometries. The critical temperature for the SIV is found to be independent of passivation integrity and dielectric confinement effect. Actual stress-free temperature (SFT) during the SIV process is also found to be different from the dielectric/cap layer deposition temperature or the final annealing temperature of the metallization, and it can be evaluated analytically once the activation energy, temperature exponent and critical temperature are determined experimentally. The smaller actual SFT indicates that a strong stress relaxation occurs before the high temperature storage test. Our results show that our SIV lifetime model can be used to predict the SIV lifetime in nano-interconnects.

Comparison of stress-induced voiding phenomena in copper line–via structures with different dielectric materials

“…As shown in our previous work [20], the presence of defects acts as the void nucleation site for SIV in the Cu line structure. For the Cu line-via structure considered in this work, such process-induced weak points are reported to be located at the sidewall at the via bottom due to poor diffusion barrier coverage [21].…”

Growth Mechanism for Low Temperature PVD Graphene Synthesis on Copper Using Amorphous Carbon

“…One mechanism is stress induced migration 37 or stress induced voiding 38 39 in Cu that enhance the movement of vacancies in Cu film. These voids move outwards toward the edge of the Cu film and during this movement, they combine and form bigger voids, enhancing the diffusion of hydrogen and carbon radical supply.…”

Prediction of Stress Induced Voiding Reliability in Cu Damascene Interconnect by Computer Aided Vacancy Migration Analysis

“…Typically, it is thought that a stress-free temperature of interconnects is a temperature at which final annealing is conducted or a temperature at which dielectric layer or passivation film is deposited. [18][19][20][21] Therefore we assumed that the stress-free temperature is 360 C at which dielectric layer was deposited. Calculations were performed for the case of cooling from the initial stress free temperature (360 C) to room temperature (20 C), then up to 150 C, that is a temperature at which SiV acceleration tests were conducted.…”