Stress-Dependent Performance Optimization of Reconfigurable Silicon Nanowire Transistors

Baldauf, Tim; Heinzig, André; Trommer, Jens; Mikolajick, Thomas; Weber, Walter M.

doi:10.1109/led.2015.2471103

Cited by 17 publications

(8 citation statements)

References 12 publications

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“…In this respect, the most common approach is utilizing metal-semiconductor heterostructures embedded in a SBFET. [15] In this configuration, RFETs have already been fabricated based on Si, [4,8,16] Ge, [17][18][19] and also on 2D layered systems, like WSe 2 [20,21] or MoTe 2 , [22,23] and recently with black phosphorous. [24] Latest generation RFETs facilitate a device layout with three independent top-gates to induce additional energy barriers in the channel, enabling an even more effective suppression of the undesired charge carrier type and therefore favoring n-or p-type operation, respectively.…”

mentioning

confidence: 99%

Reconfigurable Complementary and Combinational Logic Based on Monolithic and Single‐Crystalline Al‐Si Heterostructures

Böckle

Sistani

Bažíková

et al. 2022

Adv Elect Materials

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Modern society is highly depending and relying on electronic computing devices, as for example, employed in efficient servers, personal computers, and mobiles, and currently being explored toward the realization of emerging computing paradigms, such as "artificial intelligence" and the "Internet of Things". [1] A key enabler for these paradigms is the complementary metal-oxide-semiconductor (CMOS) technology, which utilizes the concept of complementary n-and p-type field-effect transistors (FET) to construct Boolean logic gates. Importantly, in CMOS technology the logic functions are fixed by the physical layout of interconnects and the definition of doped regions and thus do not allow for a flexible alteration of the circuits after production. The continuous shrinking of feature sizes of these Si metal-oxide-semiconductor field-effect transistors (MOSFETs) has been providing performance enhancement and higher power efficiency throughout the last decades. However, classical scalability is limited [2] and the static nature of the MOSFET primitives was not developed to provide runtimeadaptability as required for new circuit paradigms. A concept to overcome the static nature in CMOS technology and reduce overall circuit area and power consumption are reconfigurable FETs (RFETs), [3][4][5] encompassing a broad family of devices that enable a reconfiguration of the dominant carrier type based on either Schottky-barrier field-effect transistors (SBFET), [4,[6][7][8][9] or steep slope band-to-band tunneling transistors (TFET), [10][11][12][13] capable of dynamically altering the device operation between n-and p-type. This device concept thus gives rise to a paradigm change where devices, circuits, and even systems are actively and dynamically reconfigured after manufacturing or, as particularly noteworthy, even during run-time, enabling an adaption to the needed logic function of a circuit. Importantly, this "fine-grain" approach is fundamentally different to the already available "coarse-grain" approach followed in field programmable gate arrays (FPGAs) [14] based on signal routing to predefined logic blocks, resulting in high latency in data Metal-semiconductor heterostructures providing geometrically reproducible and abrupt Schottky nanojunctions are highly anticipated for the realization of emerging electronic technologies. This specifically holds for reconfigurable field-effect transistors, capable of dynamically altering the operation mode between n-or p-type even during run-time. Targeting the enhancement of fabrication reproducibility and electrical balancing between operation modes, here a nanoscale Al-Si-Al nanowire heterostructure with single elementary, monocrystalline Al leads and sharp Schottky junctions is implemented. Utilizing a three top-gate architecture, reconfiguration on transistor level is enabled. Having devised symmetric on-currents as well as threshold voltages for n-and p-type operation as a necessary requirement to exploit complementary reconfigurable circuits, selected implementations of log...

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confidence: 99%

Reconfigurable Complementary and Combinational Logic Based on Monolithic and Single‐Crystalline Al‐Si Heterostructures

Böckle

Sistani

Bažíková

et al. 2022

Adv Elect Materials

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“…By introducing a plurality of gate electrodes to Schottky-barrier nanowire FETs, reconfigurable nanowire FETs can be constructed (Figure , first row), which have multiple operation states. ,,− For reconfigurable FETs, unipolar p - and n -type conduction can be merged into a single nanowire device, which is realized by programming an electric signal. Specifically, with a single semiconducting channel that can conduct both electrons and holes, undesired charge carriers can be filtered through the transistor by applying a local electric potential …”

Section: Fundamental Electronic Properties Of Single Nanowire Transis...mentioning

confidence: 99%

Nanowire Electronics: From Nanoscale to Macroscale

et al. 2019

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Semiconductor nanowires have attracted extensive interest as one of the best-defined classes of nanoscale building blocks for the bottom-up assembly of functional electronic and optoelectronic devices over the past two decades. The article provides a comprehensive review of the continuing efforts in exploring semiconductor nanowires for the assembly of functional nanoscale electronics and macroelectronics. Specifically, we start with a brief overview of the synthetic control of various semiconductor nanowires and nanowire heterostructures with precisely controlled physical dimension, chemical composition, heterostructure interface, and electronic properties to define the material foundation for nanowire electronics. We then summarize a series of assembly strategies developed for creating well-ordered nanowire arrays with controlled spatial position, orientation, and density, which are essential for constructing increasingly complex electronic devices and circuits from synthetic semiconductor nanowires. Next, we review the fundamental electronic properties and various single nanowire transistor concepts. Combining the designable electronic properties and controllable assembly approaches, we then discuss a series of nanoscale devices and integrated circuits assembled from nanowire building blocks, as well as a unique design of solution-processable nanowire thin-film transistors for high-performance large-area flexible electronics. Last, we conclude with a brief perspective on the standing challenges and future opportunities.

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“…Later, fully symmetric electrical characteristics of RFETs and proof of complementary circuits built thereof were presented also by Heinzig et al (2013). Symmetry in the IV characteristics was reached by the application of stressors (figures 15 and 16(a)) to adjust the tunneling probability for both electrons and holes (Baldauf et al 2015) (figure 16(b)). In the second approach, (B) (see figure 14(b)) both Schottky junctions are steered simultaneously accumulating either injected holes (V PG < 0) or electrons (V PG > 0) in the channel and thus programming the device polarity.…”

Section: Reconfigurable and Polarity Control Nanowire Fetsmentioning

confidence: 99%

“…Silicon nanowires can be smoothened and trimmed in diameter by the formation of a sacrificial self-limited oxide (Liu et al 1994, Kedzierski et al 1999, Morita et al 2010. Figure 31 shows process simulation results of a dry oxidation at 875 °C (Baldauf et al 2015). This process is often combined with a high temperature hydrogen anneal that helps to reconstruct the nanowire surface smoothing out the line edge roughness.…”

Section: Top-down Nanowire Fabricationmentioning

confidence: 99%

Silicon and germanium nanowire electronics: physics of conventional and unconventional transistors

Weber

Mikolajick

2017

Rep. Prog. Phys.

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Research in the field of electronics of 1D group-IV semiconductor structures has attracted increasing attention over the past 15 years. The exceptional combination of the unique 1D electronic transport properties with the mature material know-how of highly integrated silicon and germanium technology holds the promise of enhancing state-of-the-art electronics. In addition of providing conduction channels that can bring conventional field effect transistors to the uttermost scaling limits, the physics of 1D group IV nanowires endows new device principles. Such unconventional silicon and germanium nanowire devices are contenders for beyond complementary metal oxide semiconductor (CMOS) computing by virtue of their distinct switching behavior and higher expressive value. This review conveys to the reader a systematic recapitulation and analysis of the physics of silicon and germanium nanowires and the most relevant CMOS and CMOS-like devices built from silicon and germanium nanowires, including inversion mode, junctionless, steep-slope, quantum well and reconfigurable transistors.

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Stress-Dependent Performance Optimization of Reconfigurable Silicon Nanowire Transistors

Cited by 17 publications

References 12 publications

Reconfigurable Complementary and Combinational Logic Based on Monolithic and Single‐Crystalline Al‐Si Heterostructures

Reconfigurable Complementary and Combinational Logic Based on Monolithic and Single‐Crystalline Al‐Si Heterostructures

Nanowire Electronics: From Nanoscale to Macroscale

Silicon and germanium nanowire electronics: physics of conventional and unconventional transistors

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