Strained-Si Channel Super-Self-Aligned Back-Gate/Double-Gate Planar Transistors

Lin, Hao; Liu, Haitao; Kumar, Amitesh; Avci, Uygar E.; Delden, Jay S. Van; Tiwari, Sandip

doi:10.1109/led.2007.896896

Cited by 3 publications

(2 citation statements)

References 11 publications

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“…This provides an additional degree of freedom allowing for more flexible circuit design over using single-gate or common-gate counterparts, a feature especially important for adaptive circuit design. Devices with these attributes have been demonstrated by a number of groups [10], [11] in self-aligned geometry.…”

Section: Double-gate Mosfet and Its Modeling For Simulationsmentioning

confidence: 99%

Adaptive Circuit Design Using Independently Biased Back-Gated Double-Gate MOSFETS

Kim

Solomon

Tiwari

2012

IEEE Trans. Circuits Syst. I

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A new adaptive circuit design approach is proposed and analyzed employing independently biased back-gated Double-Gate MOSFET (DGMOSFET) devices. Threshold voltage tuning using back-gate of the DGMOSFET was compared with a conventional body-bias method. The technique is a promising solution to control the transistor's threshold voltage while reducing undesirable effects at the sub-50-nm device technology nodes. An automatic adaptive circuit for threshold voltage tuning was implemented using DGMOSFET devices in 45 nm CMOS technology. Simulation results show that this circuit compensates for static and dynamic variations. This adaptation approach using DGMOSFETs along with adaptive supply voltage scaling allows simultaneous optimization of power and performance according to application-specific workload and requirements. Simulation results using a 45 nm CMOS technology indicate that this adaptive circuit design can provide 50% higher performance for the same energy, or consume 40% less energy for the same performance. In contrast to conventional methods which only employ dynamic voltage scaling, adaptive tuning of threshold voltages reduces power consumption while maintaining its noise margin.Index Terms-Adaptive circuit, body bias, double-gate MOSFET, dynamic voltage scaling, noise margin, optimization of power and performance, static and dynamic variation.

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Section: Double-gate Mosfet and Its Modeling For Simulationsmentioning

confidence: 99%

Adaptive Circuit Design Using Independently Biased Back-Gated Double-Gate MOSFETS

Kim

Solomon

Tiwari

2012

IEEE Trans. Circuits Syst. I

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“…Traditionally, strained-Si (s-Si) layer is included for its advantageous characteristics such as enhanced carrier mobility, overshoot of carrier velocity, and higher ON current . [1][2][3][4][5][6] With the help of layer transfer technique, 7 biaxial-tensile strain is induced in Silicon material by developing the Silicon material over a Si 1 − X Ge X buffer material with bigger in plane lattice constant than the Silicon material, which is grown on Silicon on Insulator (SOI) body. Later, by selective etching process, the strained-Si layer is transferred on the surface of the SOI substrate by removing the Si 1 − X Ge X layer.…”

Section: Introductionmentioning

confidence: 99%

Analytical modeling of subthreshold current and swing of strained‐Si graded channel dual material double gate MOSFET with interface charges and analysis of circuit performance

Suddapalli

Nistala

2020

Int J Numerical Modelling

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In this paper, a two-dimensional (2-D) center channel potential based subthreshold current (SC) and subthreshold swing (SS) are developed analytically for strained-Si (s-Si) graded-channel dual-material double gate (GC-DMDG) MOSFET with interface charges. The proposed analytical model is extracted by solving 2-D Poisson equation in s-Si graded-channel using appropriate boundary conditions. The analytical 2-D model includes effects of various MOSFET parameters such as s-Si channel length, strain in the silicon substrate, and oxide interface charge density with damaged length by extensively analyzing channel potential, SC, and SS. Also, the subthreshold characteristics of the proposed s-Si GC-DMDG MOSFET demonstrate superior performance over s-Si graded channel double gate MOSFET. The numerical results obtained using TCAD of the proposed DG MOSFET are validated with the results attained from proposed analytical model. Moreover, the performance of CMOS inverter using s-Si GC-DMDG MOSFET is evaluated for different device parameters. It is investigated that the proposed s-Si GC-DMDG MOSFET has better noise margin than s-Si GC-DG MOSFET.

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Scale changes in electronics: Implications for nanostructure devices for logic and memory and beyond

Kim

Lee

Rubin

et al. 2013

Solid-State Electronics

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Strained-Si Channel Super-Self-Aligned Back-Gate/Double-Gate Planar Transistors

Cited by 3 publications

References 11 publications

Adaptive Circuit Design Using Independently Biased Back-Gated Double-Gate MOSFETS

Adaptive Circuit Design Using Independently Biased Back-Gated Double-Gate MOSFETS

Analytical modeling of subthreshold current and swing of strained‐Si graded channel dual material double gate MOSFET with interface charges and analysis of circuit performance

Scale changes in electronics: Implications for nanostructure devices for logic and memory and beyond

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