Analytical modeling of subthreshold current and swing of strained‐Si graded channel dual material double gate MOSFET with interface charges and analysis of circuit performance

Abstract

In this paper, a two-dimensional (2-D) center channel potential based subthreshold current (SC) and subthreshold swing (SS) are developed analytically for strained-Si (s-Si) graded-channel dual-material double gate (GC-DMDG) MOSFET with interface charges. The proposed analytical model is extracted by solving 2-D Poisson equation in s-Si graded-channel using appropriate boundary conditions. The analytical 2-D model includes effects of various MOSFET parameters such as s-Si channel length, strain in the silicon substrate, and oxide interface charge density with damaged length by extensively analyzing channel potential, SC, and SS. Also, the subthreshold characteristics of the proposed s-Si GC-DMDG MOSFET demonstrate superior performance over s-Si graded channel double gate MOSFET. The numerical results obtained using TCAD of the proposed DG MOSFET are validated with the results attained from proposed analytical model. Moreover, the performance of CMOS inverter using s-Si GC-DMDG MOSFET is evaluated for different device parameters. It is investigated that the proposed s-Si GC-DMDG MOSFET has better noise margin than s-Si GC-DG MOSFET.

Variability Analysis of Graded Channel Dual Material-double Gate Strained-silicon MOSFET With fixed Charges

“…In this technique, the biaxial-tensile strain is developed in silicon layer by growing a silicon layer on the relaxed Si (1−X) Ge (X) layer, which is developed on silicon on insulator (SOI) material. In nano scaled MOSFETs, interface traps are generated at s-Si/Oxide (s-Si/SiO 2 ) interface due to the electric field in s-Si devices [8]- [10]. Hence, the performance of s-Si MOSFET deteriorates in terms of threshold voltage and short channel effects (SCEs).…”

Analog/RF Performance of Triple Material Gate Stack-Graded Channel Double Gate-Junctionless Strained-silicon MOSFET with Fixed Charges

“…In this method, the biaxial-tensile strain is introduced in silicon material by growing the silicon material on the relaxed Si (1−X) Ge (X) material, which is developed on the Silicon-on-insulator (SOI) layer. When device operates in nano-scaled regime, fixed charges are created at Oxide/s-Si (SiO 2 /s-Si) interface due to the lateral electric field in s-Si MOSFETs [8]- [9]. Thereby, the performance of MOSFET deteriorates in terms of threshold voltage and channel potential.…”