Strain and layout management in dual channel (sSOI substrate, SiGe channel) planar FDSOI MOSFETs

Andrieu, F.; Cassé, M.; Baylac, E.; Perreau, P.; Nier, O.; Rideau, D.; Berthelon, R.; Pourchon, F.; Pofelski, Alexandre; Salvo, B. De; Gallon, C.; Mazzocchi, V.; Barge, D.; Gaumer, C.; Gourhant, Olivier; Cros, A.; Barral, V.; Ranica, R.; Planes, N.; Schwarzenbach, W.; Richard, Evelyne; Josse, E.; Weber, O.; Arnaud, F.; Vinet, M.; Faynot, O.; Haond, M.

doi:10.1109/essderc.2014.6948769

Cited by 18 publications

(16 citation statements)

References 13 publications

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“…When combined with uni-axially strained raised SiGe source/drain, it requires a rigorous 3D mechanical simulation methodology to obtain realistic and layout dependent simulations [8], [9]. As illustrated Fig.…”

Section: B Modeling Of Strainmentioning

confidence: 99%

TCAD modeling challenges for 14nm FullyDepleted SOI technology performance assessment

Tavernier

Pereira

Nier

et al. 2015

2015 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)

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This paper reviews the main challenges for the TCAD of 14nm Fully-Depleted Silicon-On-Insulator (FDSOI) technology performance assessment. Thanks to a multi-scale approach combining extensive electrical characterization and advanced solvers simulations, ensuring deep physical insight, we provide TCAD simulation framework for device layout optimization, strain engineering and device reliability assessment.

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Section: B Modeling Of Strainmentioning

confidence: 99%

TCAD modeling challenges for 14nm FullyDepleted SOI technology performance assessment

Tavernier

Pereira

Nier

et al. 2015

2015 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)

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“…Hole mobility is higher for pMOSFETs using compressive Si or compressive SiGe channels [2][3][4][5][6] whereas electron mobility is higher for nMOSFETs using tensile Si [3,5,6]. The interest of such strain boosters has been demonstrated on bulk, and Fully-Depleted architecture such as planar FDSOI technologies (Fig.1).…”

Section: Introductionmentioning

confidence: 95%

“…The use of mobility boosters is an effective way to improve CMOS performance and reduce power consumption [1][2][3][4][5][6]. Hole mobility is higher for pMOSFETs using compressive Si or compressive SiGe channels [2][3][4][5][6] whereas electron mobility is higher for nMOSFETs using tensile Si [3,5,6].…”

Section: Introductionmentioning

confidence: 99%

“…For biaxial stress level larger than 1.4 GPa, the μ(σ) curve exhibits a saturation, whereas uniaxial stress (along the transport direction) enables to further increase the electron mobility (up to + 100 % at 3 GPa). The current technology for Smart Cut TM sSOI presents stress levels as high as + 1.4 GPa, offering significant nFET performance boost: + 20 % in the ON state current (I ON ) [4].…”

Section: Introductionmentioning

confidence: 99%

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New insights on strained-Si on insulator fabrication by top recrystallization of amorphized SiGe on SOI

Bonnevialle

Reboh

Grenouillet

et al. 2015

EUROSOI-ULIS 2015: 2015 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon

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We demonstrate the fabrication of strained Si-OnInsulator (sSOI) using a relaxation process of a compressive SiGe layer on SOI, and the transfer of lattice parameter from the relaxed SiGe to the Si layer. This process is based on a partial amorphization and recrystallization of the SiGe/Si stack. We used HRXRD (High Resolution X-Ray Diffraction) and TEM (Transmission Electron Microscopy) to characterize the microstructure of the layers. Strain and Stress evolutions throughout the process were determined using Raman spectroscopy and wafer bow measurements. Using a stack of 40 nm Si 0.7 Ge 0.3 on 9 nm Si, we obtained tensile Si layer having a stress of + 1.6 GPa which corresponds to a 80% lattice parameter transfer from SiGe to Si.

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“…We then fabricated core and I/O transistors on both SOI and sSOI substrates. They integrate a thin and a thick HK oxide respectively [4,5]. The gate length is scaled down to 28nm for core devices.…”

Section: Introductionmentioning

confidence: 99%

Performance and reliability of strained SOI transistors for advanced planar FDSOI technology

Besnard¹,

Garros²,

Subirats³

et al. 2015

2015 IEEE International Reliability Physics Symposium

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In this paper, we investigate the potential of strained Silicon-On-Insulator (sSOI) for the future advanced CMOS nodes. Strained FDSOI depicts a 30% higher performance in term of I ON /I OFF thanks to higher mobility. Changes in band structure reduce the gate leakage and devices depict superior HC reliability at same drive current. The better interface quality with sSi layer leads to higher immunity to dangling bonds generation. Strain integration does not affect BTI and breakdown reliability.

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Strain and layout management in dual channel (sSOI substrate, SiGe channel) planar FDSOI MOSFETs

Cited by 18 publications

References 13 publications

TCAD modeling challenges for 14nm FullyDepleted SOI technology performance assessment

TCAD modeling challenges for 14nm FullyDepleted SOI technology performance assessment

New insights on strained-Si on insulator fabrication by top recrystallization of amorphized SiGe on SOI

Performance and reliability of strained SOI transistors for advanced planar FDSOI technology

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