Statistics of electromigration early failures in Cu/oxide dual-damascene interconnects

Ogawa, Ennis T.; Lee, K.-D.; Matsuhashi, Hideki; Ko, Kil Soo; Justison, Patrick; Ramamurthi, A.N.; Bierwag, A. J.; Ho, Paul S.; Blaschke, V.; Havemann, R.H.

doi:10.1109/relphy.2001.922925

Cited by 38 publications

(13 citation statements)

References 23 publications

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“…However, the realities of fabricating Cu-based interconnects necessitate a transition to a damascene-based integration strategy rather than the etch/lift-off approach used for Al interconnects. This new interconnect architecture has been found to possess certain vulnerabilities to voiding under electromigration stress in and around its Cu vias [32], [33]. Similar vulnerabilities to voiding have been found under thermomechanical stress [28], [34]- [47].…”

Section: A Concerns Dominated By Interface Diffusion Mechanisms 1) Ementioning

confidence: 84%

Interface Reliability Assessments for Copper/Low-k Products

Hartfield

Ogawa

Park

et al. 2004

IEEE Trans. Device Mater. Relib.

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Multiple new materials are being adopted by the semiconductor industry at a rapid rate for both semiconductor devices and packages. These advances are driving significant investigation into the impact of these materials on device and package reliability. Active investigation is focused on the impact of back-end-of-line (BEOL) processing on Cu/low-k reliability. This paper discusses Cu/low-k BEOL interfacial reliability issues and relates key items from the assembly process and packaging viewpoint that should be managed in order to prevent adverse assembly impact on BEOL interfacial reliability. Reliability failure mechanisms discussed include interface diffusion-controlled events such as the well-known example of Cu electromigration (EM), as well as stress-migration voiding. Interface defectivity impact on dielectric breakdown and leakage is discussed. Lastly, assessments of assembly impact on these Cu/low-k interfacial concerns are highlighted.

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Section: A Concerns Dominated By Interface Diffusion Mechanisms 1) Ementioning

confidence: 84%

Interface Reliability Assessments for Copper/Low-k Products

Hartfield

Ogawa

Park

et al. 2004

IEEE Trans. Device Mater. Relib.

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“…Chain structures have been used for reliability studies of BEOL wiring [15,16], and for studies of bump interconnects [8,9,17]. The "weakest link" analytical model has been used in the BEOL studies as well as studies of fine-line interconnects [18].…”

Section: Electromigration Test Methodologymentioning

confidence: 99%

Characterization of Micro-Bump C4 Interconnects for Si-Carrier SOP Applications

Wright

Polastre

Gan³

et al.

56th Electronic Components and Technology Conference 2006

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This paper describes yield, contact resistance, and preliminary reliability test results on micro-bump C4 interconnects in modules containing Si-chips and Si-carriers. Modules containing eutectic PbSn or SnCu bump solders were fabricated with high yield, with similar interconnect contact resistances for both solders. The contact resistance and reliability test results to date suggest that reliable, highcurrent, high-density bump interconnections can be achieved for Si-carrier technology. IntroductionSilicon-carrier System-on-Package (SOP) technology offers much promise for a number of electronic packaging applications [1,2]. Several key technology components are required to enable this technology, including Si through-vias, high-density wiring, and high-density, controlled-collapse chip-connection (C4) interconnects between the silicon chip and silicon carrier (micro-bumps). Micro-bump flip-chip interconnections allow high wiring density in the Si-carrier, as compared to organic or ceramic substrates, and also enable high-performance signal and power connections. Although small C4 bumps were first fabricated in the 1960's, the packaging industry is only now moving toward bump arrays smaller than standard 100 µm diameter on 200 µm pitch (4-on-8). When combined with high-density wiring in the Sicarrier, high-density interconnections allow increased signal bandwidth between multiple chipsets, with little or no reduction in signal quality. Of equal importance, a high density array of power and ground interconnections allows improvements in power distribution design, especially for applications involving power cycling. Questions remain concerning the viability of fine-pitch bump arrays, particularly for package components with different thermal expansion coefficients (CTE). For Sn-based solders, there is strong formation of brittle intermetallic compounds (IMCs) over time. As the bump size decreases, the ratio of volume to surface area decreases, so the IMCs will constitute a larger portion of the bump.

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“…In addition, long lines increase the probability that there exist "defects" within the structures that can act as void nucleation and growth points (triple-points, "contamination patches" [14], initial voids, etc.). Thus, long via chains sample the worst-case-scenario, and open-circuit failures follow statistics given by the weakest-link or Weibull statistics [7], [15], [16]. Thus, the failure criteria used in this study was an open-circuit failure.…”

Section: Data Analysis Methodologymentioning

confidence: 99%