Statistical Modeling with the Virtual Source MOSFET Model

Yu, Li; Lan, Wei; Elfadel, Ibrahim M.; Antoniadis, D.A.; Boning, Duane S.

doi:10.7873/date.2013.296

Cited by 8 publications

(8 citation statements)

References 12 publications

(17 reference statements)

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“…In nanoscale technologies, IC testing has contributed to a significant portion of the total manufacturing cost to the point that it is now almost impossible to cover all I-V measurements for every on-chip monitoring device on each die in a wafer. Existing statistical parameter extraction methods such as the backward propagation of variance (BPV) [3] [4] are advantageous only when the number of measurements is larger than the number of model parameters. They also impose the stringent constraint that extracted parameters must be statistically uncorrelated.…”

Section: Introductionmentioning

confidence: 99%

Remembrance of Transistors Past

Saxena

Hess

et al. 2014

Proceedings of the 51st Annual Design Automation Conference

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In this paper, we propose a novel MOSFET parameter extraction method to enable early technology evaluation. The distinguishing feature of the proposed method is that it enables the extraction of an entire set of MOSFET model parameters using limited and incomplete IV measurements from on-chip monitor circuits. An important step in this method is the use of maximum-a-posteriori estimation where past measurements of transistors from various technologies are used to learn a prior distribution and its uncertainty matrix for the parameters of the target technology. The framework then utilizes Bayesian inference to facilitate extraction using a very small set of additional measurements. The proposed method is validated using various past technologies and post-silicon measurements for a commercial 28-nm process. The proposed extraction could also be used to characterize the statistical variations of MOSFETs with the significant benefit that some constraints required by the backward propagation of variance (BPV) method are relaxed.

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Section: Introductionmentioning

confidence: 99%

Remembrance of Transistors Past

Saxena

Hess

et al. 2014

Proceedings of the 51st Annual Design Automation Conference

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“…This ensemble has been generated for a given input vector but under varying process parameters. Now we formulate the problem of statistical library characterisation in input space as that of estimating f T and f S given k input vectors {ξ} = {ξ (1) , ξ (2) , ..., ξ (k) } and k ensembles of output observations {{T…”

Section: Problem Formulationmentioning

confidence: 99%

“…The problem of nominal library characterisation is to estimate f T and f S given k input vectors {ξ} = {ξ (1) , ξ (2) , ..., ξ (k) } and k output observations {T…”

Section: Problem Formulationmentioning

confidence: 99%

“…This approach will quickly become infeasible as either N LU T or N sample in a technology increases. Historically, circuit level Monte Carlo (MC) simulation has been employed to generate a number of samples in the process parameter probability space [2]. Such approach allows variability-aware analysis to be implemented with minor changes on top of existing characterization tools but requires a large number of MC runs.…”

Section: Introductionmentioning

confidence: 99%

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Statistical Library Characterization using Belief Propagation across Multiple Technology Nodes

Liu

Saxena

Hess

et al. 2015

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2015

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Abstract-In this paper, we propose a novel flow to enable computationally efficient statistical characterization of delay and slew in standard cell libraries. The distinguishing feature of the proposed method is the usage of a limited combination of output capacitance, input slew rate and supply voltage for the extraction of statistical timing metrics of an individual logic gate. The efficiency of the proposed flow stems from the introduction of a novel, ultra-compact, nonlinear, analytical timing model, having only four universal regression parameters. This novel model facilitates the use of maximum-a-posteriori belief propagation to learn the prior parameter distribution for the parameters of the target technology from past characterizations of library cells belonging to various other technologies, including older ones. The framework then utilises Bayesian inference to extract the new timing model parameters using an ultra-small set of additional timing measurements from the target technology. The proposed method is validated and benchmarked on several production-level cell libraries including a state-of-the-art 14-nm technology node and a variation-aware, compact transistor model. For the same accuracy as the conventional lookup-table approach, this new method achieves at least 15x reduction in simulation runs.

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“…In nanoscale technologies, IC testing has contributed to a significant portion of the total manufacturing cost, to the point that it is now almost impossible to proceed with all current-voltage (I-V) measurements for every on-chip monitoring device on each die in a wafer. Existing statistical parameter extraction methods such as the Backward Propagation of Variance (BPV) [3,4] are advantageous only when the number of measurements is larger than the number of model parameters. They also typically impose the stringent constraint that extracted parameters must be statistically uncorrelated.…”

mentioning

confidence: 99%