Statistical analysis of random telegraph noise in digital circuits

Abstract

Random telegraph noise (RTN) has become an important reliability issue at the sub-65nm technology node. Existing RTN simulation approaches mainly focus on single trap induced RTN and transient response of RTN, which are usually time-consuming for circuit-level simulation. This paper proposes a statistical algorithm to study multiple traps induced RTN in digital circuits, to show the temporal distribution of circuit delay under RTN. Based on the simulation results we show how to protect circuit from RTN. Bias dependence of RTN is also discussed.

Analog-circuit NBTI degradation and time-dependent NBTI variability: An efficient physics-based compact model

“…Advanced digital-stress NBTI or random telegraph noise models [4][5][6][7][8][9] are based on capture-emission-time (CET) maps or otherwise exploit the fact that the stress voltage takes on only two values. In contrast, the continuous stress voltage levels of analog signals necessitate a more complex model that takes into account extensive information about the defect dynamics: The Markov two-state NBTI model [3] is based on a differential equation describing defect charging.…”