Bias temperature instability (BTI) and hotcarrier degradation (HCD) are among the most important reliability issues but are typically studied independently in an idealized setting. However, even though it is well understood that mixed BTI/HC degradation corresponds to a realistic scenario, there is only a limited number of studies available on the impact of mixed stress conditions. In this first part of the work, we present a thorough experimental study of the impact of mixed stress conditions on SiON pMOSFET characteristics, which contain a study at the single defect level. We focus on the contribution of single defects to the recoverable component of degradation. From an electrostatic point of view, recovery after mixed negative BTI (NBTI)/HC stress is typically attributed to charge carrier emissions by oxide defects near the source, which have been charged during stress. However, the experimental characterization of recovery after different stress conditions provides strong evidence that even defects located in the vicinity of the source can remain uncharged after mixed NBTI/HC stress, and thus do not contribute to the recovery signal. Consequently, the recoverable component can be negligibly small after certain stress conditions, which leads to the conclusion that a simple electrostatic model does not properly describe the behavior of recovery after mixed NBTI/HC stress.Index Terms-Device reliability, hot-carrier degradation (HCD), mixed-mode stress, negative bias temperature instability (NBTI), pMOSFET, single oxide defects, timedependent defect spectroscopy (TDDS). I. INTRODUCTIONB IAS temperature instability (BTI) and hot-carrier degradation (HCD) affect the performance of metal-oxide-

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Characterizing mixed hot-carrier/bias temperature instability (BTI) degradation in full {V G , V D } bias space is a challenging task. Therefore, studies usually focus on individual degradation mechanisms, such as BTI and hot-carrier degradation (HCD). However, a simple superposition of these mechanisms at an arbitrary {V G , V D } combination often fails to predict the cumulative damage. We experimentally acquired a large data set covering the full bias space of a pMOSFET which allows us to obtain detailed degradation and recovery maps. Our models for describing oxide and interface defects provide physical insights into the underlying mechanisms and a possible interplay between the degradation modes. Additionally, we perform a dedicated experiment to reveal the implications of different stress regimes onto the various types of defects by switching BTI and HCD stress conditions. The results clearly reveal the conceptual limits of the assumption of independent degradation regimes. Index Terms-Bias temperature instability (BTI), defect modeling, full bias map, hot-carrier degradation (HCD), mixed-mode stress, reliability. I. INTRODUCTION A SSESSING the reliability of a technology typically focuses on idealized device degradation modes, such as bias temperature instability (BTI) and hot-carrier degradation (HCD). Each of these degradation modes is usually assessed in

Given the rapid recovery of the degradation induced by bias-temperature stress, the understanding and modeling of NBTI has been a challenge for nearly half a century. With the introduction of the time-dependent defect spectroscopy (TDDS), NBTI could be studied at the single defect level, confirming that it is dominated by a collection of first-order reactions rather then the previously invoked reaction-diffusion mechanism. The most intriguing feature of these first-order processes is the wide distribution of their time constants, which can be visualized in capture/emission time (CET) maps. In the following we clarify the microscopic link between individual defects seen in TDDS studies and the response of a large ensemble visible in the CET maps. In particular, we show how the distribution of the individual defect parameters can be extracted from measurements on large-area devices.

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We experimentally and theoretically investigate the NBTI degradation of pMOS devices due to analog stress voltages and thus go beyond existing NBTI studies for digital stress. As a result, we propose a physics-based compact model for analogstress NBTI which builds upon the extensive TCAD analysis of our ultra-short-delay experimental data. The numerical efficiency of the compact model allows its direct coupling to electric circuit simulators and permits to accurately account for NBTI degradation already during circuit design. Our model enables the calculation of the time-dependent NBTI variability of single device and of circuit performance parameters. We demonstrate our NBTI model on an operational amplifier and calculate the mean drift and variability of its offset voltage

Using time-dependent defect spectroscopy measurements on nanoscale MOSFETs, individual defects have been characterized in much greater detail than ever before. These studies have revealed the existence of metastable defect states which have a significant impact on the capture and emission time constants. For example, these defect states explain the large emission time constants observed in bias temperature measurements as well as the switching behavior of defects sensitive to gate bias changes towards accumulation. By carefully analyzing the properties of the defects contributing to random telegraph noise and the recoverable component of the bias temperature instability, it could be confirmed that both phenomena are due to the same type of defect. The most fundamental property of these defects is that their time constants are widely distributed, leading to the ubiquitous time and frequency dependence. By transferring this knowledge to large area devices, noise as well as the response to bias temperature stress and recovery can be understood in great detail.