2020
DOI: 10.1109/ted.2020.3000749
|View full text |Cite
|
Sign up to set email alerts
|

Mixed Hot-Carrier/Bias Temperature Instability Degradation Regimes in Full {V G, V D} Bias Space: Implications and Peculiarities

Abstract: Characterizing mixed hot-carrier/bias temperature instability (BTI) degradation in full {V G , V D } bias space is a challenging task. Therefore, studies usually focus on individual degradation mechanisms, such as BTI and hot-carrier degradation (HCD). However, a simple superposition of these mechanisms at an arbitrary {V G , V D } combination often fails to predict the cumulative damage. We experimentally acquired a large data set covering the full bias space of a pMOSFET which allows us to obtain detailed de… Show more

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
2
2
1

Citation Types

0
9
0

Year Published

2021
2021
2024
2024

Publication Types

Select...
7
2

Relationship

0
9

Authors

Journals

citations
Cited by 24 publications
(12 citation statements)
references
References 34 publications
0
9
0
Order By: Relevance
“…The secondary carriers from HCD can significantly enhance the recovery effect of BTI reported in the previous study, as shown in Figure 16 . This may be attributed to the substantial generation of secondary electrons in PMOS under severe V ds stress, leading to the excessive emission of NBTI traps [ 108 ]. Therefore, in establishing a mixed degradation model, it is necessary to consider the inhomogeneous BTI degradation within HCD.…”
Section: Impact Of Alternating Stress Conditionsmentioning
confidence: 99%
“…The secondary carriers from HCD can significantly enhance the recovery effect of BTI reported in the previous study, as shown in Figure 16 . This may be attributed to the substantial generation of secondary electrons in PMOS under severe V ds stress, leading to the excessive emission of NBTI traps [ 108 ]. Therefore, in establishing a mixed degradation model, it is necessary to consider the inhomogeneous BTI degradation within HCD.…”
Section: Impact Of Alternating Stress Conditionsmentioning
confidence: 99%
“…In this case, the SP (hot carriers) and MP (cold carriers) degradation mechanisms induce a cumulative effect showing that cold holes take a significant role in damaged high-voltage LDMOS [25]. Low power digital applications using thin gate-oxide devices have shown that HC and BTI damage follow an interplay that can be described by a full V GS , V DS mapping [26], modelled by an extended nonradiative multiphonon (NMPeq.+II) framework. This physical modeling has demonstrated the importance of secondary carriers and history effects with alternating HC, BTI and recovery effects at high V GS [26,27].…”
Section: Worst Case DC Degradation In N-edmosmentioning
confidence: 99%
“…Low power digital applications using thin gate-oxide devices have shown that HC and BTI damage follow an interplay that can be described by a full V GS , V DS mapping [26], modelled by an extended nonradiative multiphonon (NMPeq.+II) framework. This physical modeling has demonstrated the importance of secondary carriers and history effects with alternating HC, BTI and recovery effects at high V GS [26,27]. This was observed particularly in the p-channel MOSFET (Si bulk) structure when hot holes are involved at high |V GS | > |V DS | [26].…”
Section: Worst Case DC Degradation In N-edmosmentioning
confidence: 99%
“…HCI is also a critical factor to shift V t in compared with other reliability mechanisms [24]. The interplay of the superposed gate and drain voltages has well described the NBTI and HCI degradation of p-MOSFETs [29]. This study compared the impact of NBTI and HCI on these devices by finding the degradation level from electrical characteristics.…”
Section: Introductionmentioning
confidence: 96%