NBTI Degradation and Recovery in Analog Circuits: Accurate and Efficient Circuit-Level Modeling

Giering, Kay-Uwe; Puschkarsky, Katja; Reisinger, H.; Rzepa, G.; Rott, Gunnar Andreas; Vollertsen, R.‐P.; Jancke, Roland

doi:10.1109/ted.2019.2901907

Cited by 18 publications

(9 citation statements)

References 23 publications

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“…Furthermore, circuit simulations have been carried out employing a simplified version of the model. [ 60,111 ] Before the impact of time‐zero and time‐dependent variability on 2D electronic circuits is described in detail, the models used for the evaluation are discussed briefly.…”

Section: Performance Evaluation and Compact Modeling Of Transistorsmentioning

confidence: 99%

“…Furthermore, circuit simulations have been carried out employing a simplified version of the model. [60,111] Before the impact of time-zero and time-dependent variability on 2D electronic circuits is described in detail, the models used for the evaluation are discussed briefly. To ensure the robust operation of electronic applications, a high resilience against deviations from their ideal operational characteristics of transistors is important.…”

Section: Modeling the Impact Of Defects On Transistorsmentioning

confidence: 99%

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Perspective of 2D Integrated Electronic Circuits: Scientific Pipe Dream or Disruptive Technology?

et al. 2022

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Within the last decade, considerable efforts have been devoted to fabricating transistors utilizing 2D semiconductors. Also, small circuits consisting of a few transistors have been demonstrated, including inverters, ring oscillators, and static random access memory cells. However, for industrial applications, both time‐zero and time‐dependent variability in the performance of the transistors appear critical. While time‐zero variability is primarily related to immature processing, time‐dependent drifts are dominated by charge trapping at defects located at the channel/insulator interface and in the insulator itself, which can substantially degrade the stability of circuits. At the current state of the art, 2D transistors typically exhibit a few orders of magnitude higher trap densities than silicon devices, which considerably increases their time‐dependent variability, resulting in stability and yield issues. Here, the stability of currently available 2D electronics is carefully evaluated using circuit simulations to determine the impact of transistor‐related issues on the overall circuit performance. The results suggest that while the performance parameters of transistors based on certain material combinations are already getting close to being competitive with Si technologies, a reduction in variability and defect densities is required. Overall, the criteria for parameter variability serve as guidance for evaluating the future development of 2D technologies.

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Section: Performance Evaluation and Compact Modeling Of Transistorsmentioning

confidence: 99%

Section: Modeling the Impact Of Defects On Transistorsmentioning

confidence: 99%

Perspective of 2D Integrated Electronic Circuits: Scientific Pipe Dream or Disruptive Technology?

et al. 2022

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“…Although it has its advantages in developing advanced technology, the primary concern remains focused on the associated reliability issues. 11 The more severe device degradation mechanisms like bias temperature instability (BTI) [12][13][14][15] and hot carrier injection (HCI) 16,17 have continued to capture the attention of researchers.…”

Section: Introductionmentioning

confidence: 99%

Enabling efficient rate and temporal coding using reliability‐aware design of a neuromorphic circuit

Picardo

Shaik

Singhal

et al. 2022

Circuit Theory & Apps

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Reliability aspects such as bias temperature instability (BTI) and hot carrier injection (HCI) affecting devices in advanced CMOS-based technology have been the subject of active research in recent decades. Due to these reliability issues, various digital and analog circuits were investigated for degradation.However, circuit blocks like the neuron circuits of neuromorphic systems are not fully explored. This work is inclined toward examining the collective degradation impact of BTI and HCI due to aging in an adaptive exponential "integrate and fire" (I&F) model-based, neuromorphic neuron circuit. Detailed degradation analysis of the stimulated neuron circuit aided in identifying possible mismatches/faults associated with neuron spikes. These factors could reduce the efficiency of the neuronal circuit by potentially affecting the transmission of information in a neuromorphic system. Various performance parameters were then derived to quantify the extent of circuit deterioration. The proposed reliability-aware design aims to improve the circuit degradation through its effectiveness in alleviating the overall reliability impact. It demonstrates enhanced circuit operation in spike generation even after aging. The circuit performance is validated through simulations at "Time0" (pre-degradation) and "Aged" (post-degradation) neuron netlists, which is then compared with the proposed reliability-aware circuit.

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“…In nanoscale CMOS devices, the stochastic behavior of a few defects can have a significant impact on the reliability of devices and their circuits [1][2][3][4][5][6][7][8]. The negative bias temperature instability (NBTI) is among the most critical reliability issues and can be described by capture-emission energy (CEE) maps [3][4][5][9][10][11][12][13][14][15]. Accurately modeling the NBTI relies on a combined methodology comprising thorough CEE maps and efficient models.…”

Section: Introductionmentioning

confidence: 99%

“…An accurate estimation of the parameters of CEE distribution is crucial to enable full lifetime calculation of NBTI without measurement time extrapolation. The kinetics of defects responsible for NBTI has been explained by the random capture-emission process of charge carriers caused by oxide traps [9][10][11][12][13][14][15]18,19]. Moreover, it has been found that the recoverable component of NBTI and random telegraph signal (RTS) noise are due to same defects [19][20][21][22][23][24][25].…”

Section: Introductionmentioning

confidence: 99%

Data-Driven Modeling of Low Frequency Noise Using Capture-Emission Energy Maps

Lee

2020

Applied Sciences

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A new approach for modeling low frequency noise is presented to enable the predictions of noise behavior from negative bias temperature instability (NBTI). The noise model is based on a capture-emission energy (CEE) map describing the probability density function of widely distributed defect capture-emission activation energies. To enlarge the capture-emission energy window and to perform the accurate estimation of the recoverable component of CEE, the Gaussian mixture model (GMM) is applied to the CEE map. This approach provides an efficient identification of noise sources and an in-depth noise analysis under both stationary and cyclo-stationary conditions.

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NBTI Degradation and Recovery in Analog Circuits: Accurate and Efficient Circuit-Level Modeling

Cited by 18 publications

References 23 publications

Perspective of 2D Integrated Electronic Circuits: Scientific Pipe Dream or Disruptive Technology?

Perspective of 2D Integrated Electronic Circuits: Scientific Pipe Dream or Disruptive Technology?

Enabling efficient rate and temporal coding using reliability‐aware design of a neuromorphic circuit

Data-Driven Modeling of Low Frequency Noise Using Capture-Emission Energy Maps

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