Static Random Access Memory Characteristics of Single-Gated Feedback Field-Effect Transistors

Adv Materials Technologies

2020

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Several attempts have been made to store charges in the channel regions of silicon transistors, such as in zero-capacitor random-access memories (Z-RAMs), [7,8] metastable DRAMs (MSDRAMs), [9,10] advanced RAMs (A-RAMs), [11,12] and zeroslope and zero-impact ionization RAMs (Z 2-RAMs). [13,14] Among these, Z 2-RAMs are capable of low-voltage operation with high speed, long retention time, and nondestructive reading capability, because of the positive feedback loop. [15] However, electrostatic doping induced by gate bias is required to form a potential well, which is important for the positive feedback loop. [16,17] Although thyristor RAMs (T-RAMs) employ doping regions to form the potential well, external bias is still necessary for TRAMs to retain the stored charges. [18-20] This indispensable bias for holding the stored charges has restricted their use in quasi-nonvolatile memory applications. In this paper, we propose a fully CMOS-compatible p +-n-pn + silicon memory device to enable quasi-nonvolatile memory functionality with high speed, long retention time, and nondestructive reading capability. Using a well-defined potential well in a p +-n-p-n + silicon structure with a gated n-channel region, our device utilizes holes as majority charge carriers for the positive feedback loop, unlike TRAMs which use electrons as majority charge carriers. Hence, our quasi-nonvolatile silicon memory device can retain the charges stored in the channel region without requiring any external bias, for a long time. In addition, the positive-feedback loop enables low-voltage operation, high speed, and nondestructive reading for quasi-nonvolatile memory applications. 2. Results and Discussion A quasi-nonvolatile silicon memory device consists of p +-n-p-n + regions on a silicon-on-insulator (SOI) substrate (Figure 1a). An SiO 2 /poly-Si gate stack is located on the upper side of the n-channel region. The poly-Si gate modulates the potential barrier of the n-channel region; it controls the hole injection from the p + drain region. The p-channel region is designated to block the electron injection from the n + source region. The channel regions also form potential wells; states "1" and "0" are defined by presence and absence of excess charge carriers in the potential wells, respectively. The corresponding energy band diagrams exhibit the difference in the channel region between the two states (Figure 1b). Barrier-height modulation by carrier accumulation in the potential wells is essential for the positive feedback loop, which allows memory operations. Memory hierarchy among conventional memory technologies is one of the main bottlenecks in modern computer systems; alternative memory technologies are thus necessary for quasi-nonvolatile memory applications. Herein, a fully complementary metal-oxide-semiconductor-compatible quasi-nonvolatile memory composed of p +-n-p-n + silicon on a silicon-on-insulator substrate is presented. The quasi-nonvolatile silicon memory device demonstrates highspeed write capability (≤100 ns), long retenti...

Section: Resultsmentioning

confidence: 99%

Quasi‐Nonvolatile Silicon Memory Device

Lim

Adv Materials Technologies

2020

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“…More recently, simulation studies have demonstrated that the low standby power consumption and reliability of one-transistor SRAM (1T-SRAM) cells, each of which consists of a single-gated feedback field-effect transistor (FBFET), provide a promising possibility for the future of memory devices 17 . Compared with metal–oxide–semiconductor field-effect transistors (MOSFETs) conventionally used in SRAM cells, FBFETs, operating with a positive feedback loop mechanism, exhibit an extremely low subthreshold swing (~ 0 mV/dec), high on/off current ratios, and bi-stable states 18 – 22 .…”

Section: Introductionmentioning

confidence: 99%

One-transistor static random-access memory cell array comprising single-gated feedback field-effect transistors

Choi

et al. 2021

Sci Rep

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In this study, we fabricated a 2 × 2 one-transistor static random-access memory (1T-SRAM) cell array comprising single-gated feedback field-effect transistors and examined their operation and memory characteristics. The individual 1T-SRAM cell had a retention time of over 900 s, nondestructive reading characteristics of 10,000 s, and an endurance of 108 cycles. The standby power of the individual 1T-SRAM cell was estimated to be 0.7 pW for holding the “0” state and 6 nW for holding the “1” state. For a selected cell in the 2 × 2 1T-SRAM cell array, nondestructive reading of the memory was conducted without any disturbance in the half-selected cells. This immunity to disturbances validated the reliability of the 1T-SRAM cell array.

“…Feedback field-effect transistors (FBFETs) have recently emerged as promising devices for next-generation electronics owing to their unique characteristics that allow their application in memory and switching devices [1][2][3][4][5][6]. FBFETs having p + -n-p-n + structures are operated by positive feedback (FB) loops that are the reciprocal interaction between potential barriers and charge carriers.…”

Section: Introductionmentioning

confidence: 99%

Electrical Stability of p-Channel Feedback Field-Effect Transistors Under Bias Stresses

Kim³

2021

IEEE Access

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In this study, we examined electrical stability of the p-channel feedback field-effect transistors (FBFETs) under negative bias stress (NBS) and positive bias stress (PBS). The intact FBFETs have a subthreshold swing (SS) of 0.12 mV/dec, an on-current of ~10 -4 A, and a threshold voltage (V TH ) of -0.76 V. There is a negligible change in the on-current and SS when the FBFETs are stressed by a gate-bias voltage corresponding to an electric field of 5.4 MV/cm across the gate oxide. On the other hand, as the duration of the stress increases to 1000 s, the V TH shifts to -0.89 V and -0.67 V for NBS and PBS, respectively. The V TH was recovered to over 83% at a recovery bias voltage of 5 V. The electrical stabilities of FBFETs under NBS and PBS are discussed in this study.