Electrical Stability of p-Channel Feedback Field-Effect Transistors Under Bias Stresses

Son, Jaemin; Cho, Kyoungah; Kim, Sangsig

doi:10.1109/access.2021.3108232

Cited by 4 publications

(4 citation statements)

References 22 publications

(19 reference statements)

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“…Interface defects are responsible for the electrical instability of Si-based devices. Our previous simulation study has revealed that the interface traps substantially affect the electrical characteristics of FBFETs [25]. The dominant electrically-active interface defects are P b centers being dangling bonds of Si atoms that are bonded to three neighboring Si atoms in the bulk crystal; these centers are characterized by unpaired electrons localized in sp 3 -like silicon dangling bonds [24,26,27].…”

Section: Resultsmentioning

confidence: 99%

Gate-bias stability of triple-gated feedback field-effect transistors with silicon nanosheet channels

Heo,

Shin,

Son

et al. 2024

Nanotechnology

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In this study, we investigate the gate-bias stability of triple-gated feedback field-effect transistors (FBFETs) with Si nanosheet channels. The subthreshold swing (SS) of FBFETs increases from 0.3 mV/dec to 60 and 80 mV/dec in p- and n-channel modes, respectively, when a positive bias stress (PBS) is applied for 1000 s. In contrast, the SS value does not change even after a negative bias stress (NBS) is applied for 1000 s. The difference in the switching characteristics under PBS and NBS is attributed to the ability of the interface trapsto readily gain electrons from the inversion layer. The switching characteristics deteriorated by PBS are completely recovered after annealing at 300 °C for 10 mins, and thecharacteristics remain stable even after PBS is applied again for 1000 s.

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Section: Resultsmentioning

confidence: 99%

Gate-bias stability of triple-gated feedback field-effect transistors with silicon nanosheet channels

Heo,

Shin,

Son

et al. 2024

Nanotechnology

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“…Instead, the component diodes refresh their weights during multiplication operations. They also exhibit superior electrical stability against bias stresses (continuous input pulses), unlike other memory devices 13 , 19 – 21 , 44 , 45 . The diode array holds the binarized weight matrix semi-permanently using refresh operations while performing multiplication operations.…”

Section: Resultsmentioning

confidence: 99%

Binarized neural network of diode array with high concordance to vector–matrix multiplication

Shin,

Cho,

Kim

2024

Sci Rep

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In this study, a binarized neural network (BNN) of silicon diode arrays achieved vector–matrix multiplication (VMM) between the binarized weights and inputs in these arrays. The diodes that operate in a positive-feedback loop in their p+-n-p-n+ device structure possess steep switching and bistable characteristics with an extremely low subthreshold swing (below 1 mV) and a high current ratio (approximately 108). Moreover, the arrays show a self-rectifying functionality and an outstanding linearity by an R-squared value of 0.99986, which allows to compose a synaptic cell with a single diode. A 2 × 2 diode array can perform matrix multiply-accumulate operations for various binarized weight matrix cases with some input vectors, which is in high concordance with the VMM, owing to the high reliability and uniformity of the diodes. Moreover, the disturbance-free, nondestructive readout, and semi-permanent holding characteristics of the diode arrays support the feasibility of implementing the BNN.

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“…[ 38,39 ] In contrast, FBFETs that operate with a positive feedback mechanism have been verified for their superior operation and environmental stability that can compete with current CMOS technologies. [ 23,40–42 ] These promising results indicate that the ternary logic gates have powerful advantages for stable and low‐power future electronics. The DG FBFET‐based ternary logic gates are desirable for data‐intensive applications such as artificial intelligence, Internet of Things, etc.…”

Section: Resultsmentioning

confidence: 99%

Logic‐in‐Memory Operation of Ternary NAND/NOR Universal Logic Gates using Double‐Gated Feedback Field‐Effect Transistors

Son

Shin

Cho

et al. 2023

Adv Elect Materials

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In this study, the logic‐in‐memory operations are demonstrated of ternary NAND and NOR logic gates consisting of double‐gated feedback field‐effect transistors. The component transistors reconfigure their operation modes into n‐ or p‐channel modes by adjusting the gate biases. The highly symmetrical operation between these operation modes with an excellent on‐current ratio of 1.03 enables three distinguishable and stable logic levels in the ternary logic gates. Moreover, the ternary logic gates maintain the three logic states for several tens to hundreds of seconds under zero‐bias condition. This study demonstrates that the ternary logic gates are promising candidates for next‐generation low‐power computing systems.

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Electrical Stability of p-Channel Feedback Field-Effect Transistors Under Bias Stresses

Cited by 4 publications

References 22 publications

Gate-bias stability of triple-gated feedback field-effect transistors with silicon nanosheet channels

Gate-bias stability of triple-gated feedback field-effect transistors with silicon nanosheet channels

Binarized neural network of diode array with high concordance to vector–matrix multiplication

Logic‐in‐Memory Operation of Ternary NAND/NOR Universal Logic Gates using Double‐Gated Feedback Field‐Effect Transistors

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