One-transistor static random-access memory cell array comprising single-gated feedback field-effect transistors

Abstract

In this study, we fabricated a 2 × 2 one-transistor static random-access memory (1T-SRAM) cell array comprising single-gated feedback field-effect transistors and examined their operation and memory characteristics. The individual 1T-SRAM cell had a retention time of over 900 s, nondestructive reading characteristics of 10,000 s, and an endurance of 108 cycles. The standby power of the individual 1T-SRAM cell was estimated to be 0.7 pW for holding the “0” state and 6 nW for holding the “1” state. For a selected cell in the 2 × 2 1T-SRAM cell array, nondestructive reading of the memory was conducted without any disturbance in the half-selected cells. This immunity to disturbances validated the reliability of the 1T-SRAM cell array.

Reconfigurable Feedback Field-Effect Transistors with a Single Gate

“…In particular, due to the thermal limit of carriers, the subthreshold swing has a limit of 60 mV/dec at room temperature [3]. Various devices such as tunneling FET (TFET) [4][5][6][7] that use tunneling effect, impact ionization MOS (I-MOS) [8][9][10][11] that uses impact ionization, and feedback FET (FBFET) [12][13][14][15][16][17][18][19][20][21][22][23][24] that uses feedback phenomena have been studied to overcome these limitations.…”

“…The FBFET that was first proposed [12] modulated the potential barrier by trapping charges in gate-sidewall spacers. However, due to the spacer region's additional process and instability, structures have been proposed to dope the existing spacer region with heavy doping or replace it with an additional gate electrode [14,15]. These structures are relatively stable and can be pand n-type reconfigured in a single device with an additional gate electrode [13].…”

Dependence of latch-up and threshold voltages on channel length in single-gated feedback field-effect transistor

“…Feedback field-effect transistors (FBFETs) have been researched in various fields to be utilized in next-generation memory applications such as neuromorphic devices [1][2][3][4], one-transistor memory devices [5][6][7][8], and logic-in-memory [9,10] by utilizing a positive feedback mechanism. Among them, FBFETs have been considered promising one-transistor memory devices because of the presence of memory windows with controllable hysteresis characteristics [5][6][7][8][10][11][12][13][14][15][16][17]. However, most of the research has focused on only realizing * Author to whom any correspondence should be addressed.…”

“…the desired function by simply using the hysteresis characteristics [5][6][7][8]. However, the memory windows defined by latchup, latch-down, and threshold voltages determine the memory operation conditions such as write, hold, and read operations [4,7,8].…”

“…the desired function by simply using the hysteresis characteristics [5][6][7][8]. However, the memory windows defined by latchup, latch-down, and threshold voltages determine the memory operation conditions such as write, hold, and read operations [4,7,8]. Therefore, research related to device optimization techniques and physics analysis is required to include latchup voltage and threshold voltage variations.…”