Standard cell design in N7: EUV vs. immersion

Chava, Bharani; Río, David; Sherazi, Yasser; Trivkovic, Darko; Gillijns, Werner; Debacker, Peter; Raghavan, Praveen; Elsaid, Ahmad; Dusa, Mircea V.; Mercha, A.; Ryckaert, Julien; Verkest, D.

doi:10.1117/12.2085739

Cited by 19 publications

(16 citation statements)

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“…One way the SC designers can improve the SC pin accessibility is to intelligently design the I/O pins, which maximizes the number of access hit points for each I/O pin of the SC's [2,3]. However, the complicated MPL constraints introduce interactions among neighboring access points of different I/O pins of the SC's.…”

Section: Pin Access Optimizationmentioning

confidence: 98%

“…At the library design level, SC designers target at improving the inter-cell compatibility for all combinations of cells, regardless of what kind of placement [2]. With MPL applied to multiple layers with small feature sizes [2,3], it is difficult to guarantee that any combination of SC's is compatible with MPL coloring constraints. However, a robust library should minimize the number illegal SC's combinations that lead to MPL coloring violations.…”

Section: Library Robustness Evaluationmentioning

confidence: 99%

“…Both LELE-based and spacer-based double/multiple patterning technologies have been used in fabricating critical layers which have very dense layouts, e.g., SADP has been widely used to fabricate FinFETs while LELE-based double/triple patterning has been used to print M1 layers [2][3][4]. In the future, MPL will still be a viable lithography solution for sub-10nm technology node, either continuing pushing 193nm lithography, e.g., using quadruple patterning [5], or used along with other lithography techniques, such as extreme ultraviolet lithography (EUVL), electric beam lithography (EBL), and directed self-assembly (DSA) [6].…”

Section: Introductionmentioning

confidence: 99%

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Pushing multiple patterning in sub-10nm

Pan

Liebmann

et al. 2015

Proceedings of the 52nd Annual Design Automation Conference

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Due to elongated delay of extreme ultraviolet lithography (EUVL), the semiconductor industry has been pushing the 193nm immersion lithopgrahy using multiple patterning to print critical features in 22nm/14nm technology nodes and beyond. Multiple patterning lithography (MPL) poses many new challenges to both mask design and IC physical design. The mask layout decomposition problem has been extensively studied, first on double patterning, then on triple or even quadruple patterning. Meanwhile, many studies have shown that it is very important to consider MPL implications at early physical design stages so that the overall design and manufacturing closure can be reached. In this paper, we provide a comprehensive overview on the state-of-the-art research results for MPL, from synergistic mask synthesis to physical design. We will also discuss the open problems as to pushing multiple patterning in sub-10nm.

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Section: Pin Access Optimizationmentioning

confidence: 98%

Section: Library Robustness Evaluationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Pushing multiple patterning in sub-10nm

Pan

Liebmann

et al. 2015

Proceedings of the 52nd Annual Design Automation Conference

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“…Due to complex design-for-manufacturing constraints, there are finite options of standard cell architecture for a specific advanced technology node [6], [33], [55]. Figure 5 illustrates a 7.5-track standard cell architecture at 7 nm technology node.…”

Section: Standard Cell Architecturementioning

confidence: 99%

“…For better pin accessibility, a standard cell designer mainly focuses on increasing the vertical span of an M1 pin (assuming horizontal M2 routing tracks), which provides more hit points for each pin during routing stage [33]. In advanced technology nodes, this technique is becoming less effective due to a finite number of M2 routing tracks and pin-to-pin interference [6], [64]. To systematically evaluate pin accessibility under pin-to-pin interference and advanced manufacturing constraints, it is important to quantify pin accessibility in terms of "hit point combinations" and "hit points" simultaneously [64].…”

Section: Definition 1 (Hit Point) the Overlap Of An M2 Routing Track mentioning

confidence: 99%

Toward Unidirectional Routing Closure in Advanced Technology Nodes

Pan

2017

IPSJ Transactions on System LSI Design Methodology

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Abstract:In advanced technology nodes, unidirectional layout is strongly preferred for high-density metal layers for better manufacturability. The lithography printing of unidirectional layout can be tightly controlled with illumination source optimization and resolution enhancement techniques. Meanwhile, with the unidirectional layout, self-aligned double and quadruple patterning can be applied to achieve finer pitches beyond the resolutions limits of 193 nm lithography tools. However, unidirectional layout style introduces significant impacts on the physical design flow. Notably, unidirectional routing limits the standard cell pin accessibility, which makes manual cell layout design and optimization more and more challenging under modern standard cell architecture. In the routing phase, routing densities and resource competitions on lower metal layers are becoming increasingly high, where intelligent approaches are needed to resolve routing resource competitions for unidirectional routing closure. Moreover, post-routing optimization is inevitable to avoid significant engineering-changing-efforts for unidirectional routing under advanced manufacturing constraints. In this paper, we present a holistic approach, including standard pin access evaluation/optimization, pin access and routing co-optimization and post-routing optimization, to enable unidirectional routing closure in advanced technology nodes.

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Robust FinFET Schmitt Trigger Designs for Low Power Applications

Moraes¹,

Zimpeck²,

Meinhardt³

et al. 2020

IFIP Advances in Information and Communication Technology

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The IoT development alongside with the more pronounced impact of process variability in modern technology nodes, is the central reason to control variability impact. Given the broad set of IoT devices running on battery-oriented environments, energy consumption should be minimal and the operation reliable. Schmitt Trigger inverters are frequently used for noise immunity enhancement, and have been recently applied to mitigate radiation effects and variability impact. Yet, Schmitt Trigger operation at nominal voltage still introduces high deviation on power consumption. Thus, the main contribution of this work is to identify the relationship between transistor sizing, supply voltage, energy, and process variability robustness to achieve a minimal energy consumption circuit while keeping robustness. On average, scenarios with a lower supply voltage applied on layouts with a smaller number of fins, presented adequate robustness in high variability scenarios. Exploring voltage and transistor sizing made possible a reduction of about 24.84% on power consumption.

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Standard cell design in N7: EUV vs. immersion

Cited by 19 publications

References 0 publications

Pushing multiple patterning in sub-10nm

Pushing multiple patterning in sub-10nm

Toward Unidirectional Routing Closure in Advanced Technology Nodes

Robust FinFET Schmitt Trigger Designs for Low Power Applications

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