Stacked Ge Nanosheet GAAFETs Fabrication and Strain Effects Measurement

Chu, Chun-Lin; Luo, Guang-Li; Wu, K.; Chen, Shih-Hong; Chen, Bo‐Yuan; Wu, Wen−Fa; Yeh, Wen–Kuan

doi:10.1109/vlsi-tsa48913.2020.9203617

Cited by 4 publications

(11 citation statements)

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“…3(a) [2], V GS the layer structure used for Ge channel NSFETs which uses a Ge/Si multilayer stack is shown in Fig. 3(b) [12], and Fig. 3(c) is the starting epitaxial stack used for Ge NSFET which uses a Ge/Si 0.3 Ge 0.7 stack [9], [11].…”

Section: Proposed Nsfet Design Simulation Methodology and Process Flowmentioning

confidence: 99%

“…Furthermore, the Ge/Si multilayer structure used for Ge NSFET shown in Fig. 3(b) [12] will result in a ~ 4 % lattice mismatch, resulting in a further aggravated strain relaxation issue. This limits the total height of the device (i.e., number of stacked layers vertical pitch) and restricts the number of stacked layers, vertical pitch as well as the thickness of individual layer.…”

Section: Proposed Nsfet Design Simulation Methodology and Process Flowmentioning

confidence: 99%

“…3(e). The process steps are directly transferrable from Ge FinFET [12] fabrication as well as traditional Si/SiGe NSFETs [5], except for the selective etch chemistry which can be performed using dry or wet etch process. The Ge/AlAs selective etch for Ge NS release can be carried out using a BOE/HF wet-etch with an extremely high selectivity of ~10 5 :1 resulting in a minimal loss of the Ge active layer, significantly better than existing ~ 150:1 by RIE/dry etch [2], [13], [14] of Si NS.…”

Section: Proposed Nsfet Design Simulation Methodology and Process Flowmentioning

confidence: 99%

“…The proposed Ge/AlAs lattice matched NSFET configuration can provide the necessary material properties (high mobility and defect free active channel) to enable stacking N beyond 4. The proposed Ge/AlAs and Ge/InGaAs NSFET designs are benchmarked with recent experimental reports of Ge, SiGe, GeSn and Si based p-GAA devices in Table II [9], [12], [17], [33]- [38]. In addition, due to the compatibly of the Ge NSFET stack with III-V materials like AlAs and InGaAs, a common Ge/InGaAs multilayer stack has potential to be utilized to fabricate InGaAs based n-NSFET and Ge based p-NSFET with complementary etch-chemistry, thus forming high electron and hole mobility channels for low power cointegrated CMOS [15].…”

Section: Circuit Analysis Of Proposed P-nsfet Using Different Design ...mentioning

confidence: 99%

“…Thus, along with a Ge channel for higher hole mobility, a Ge p-NSFET process which provides lattice matched epitaxial growth as well as superior etch selectivity between active Ge layers and the sacrificial layers is required. Recently, Ge/SiGe epitaxial growth-based investigations for Ge p-GAA FETs have been reported through simulations as well as by experiment [5], [9]- [12].…”

Section: Introductionmentioning

confidence: 99%

See 4 more Smart Citations

Germanium Nanosheet-FETs Scaled to Subnanometer Node Utilizing Monolithically Integrated Lattice Matched Ge/AlAs and Strained Ge/InGaAs

Joshi

Karthikeyan

Hudait

2023

IEEE Trans. Electron Devices

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is possible, and a significant boost in ION (~ 4×) is obtained with 8 layers despite of parasitics induced selfloading. In applications requiring high drive current, increasing the number of stacked Ge nanosheets is the most efficient design pathway to improve circuit delay and area-delay-product. This system shows suitability for low-power and high-performance applications for dimensions down to N0.7, where the ION is ~ 0.6mA/µm and the SS is 81 mV/dec.

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Section: Proposed Nsfet Design Simulation Methodology and Process Flowmentioning

confidence: 99%

Section: Proposed Nsfet Design Simulation Methodology and Process Flowmentioning

confidence: 99%

Section: Proposed Nsfet Design Simulation Methodology and Process Flowmentioning

confidence: 99%

Section: Circuit Analysis Of Proposed P-nsfet Using Different Design ...mentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Germanium Nanosheet-FETs Scaled to Subnanometer Node Utilizing Monolithically Integrated Lattice Matched Ge/AlAs and Strained Ge/InGaAs

Joshi

Karthikeyan

Hudait

2023

IEEE Trans. Electron Devices

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Carrier Recombination Dynamics of Surface-Passivated Epitaxial (100)Ge, (110)Ge, and (111)Ge Layers by Atomic Layer Deposited Al₂O₃

Hudait

Johnston

Das

et al. 2023

ACS Appl. Electron. Mater.

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Germanium (Ge) and its heterostructures with compound semiconductors offer a unique optoelectronic functionality due to its pseudo-bandgap nature, that can be transformed to a direct bandgap material by providing strain and/or mixing with tin. Moreover, two crystal surfaces, (100)Ge and (110)Ge, that are technologically important for ultralow power fin or nanosheet transistors, could offer unprecedented properties with reduced surface defects after passivating these surfaces by atomic layer deposited (ALD) dielectrics. In this work, the crystallographically oriented epitaxial Ge/AlAs heterostructures were grown and passivated with ALD Al2O3 dielectrics, and the microwave photoconductive decay (μ-PCD) technique was employed to evaluate carrier lifetimes at room temperature. The X-ray photoelectron spectroscopy analysis reveals no role of orientation effect in the quality of the ALD Al2O3 dielectric on oriented Ge layers. The carrier lifetimes measured using the μ-PCD technique were benchmarked against unpassivated Ge/AlAs heterostructures. Excitation wavelengths of 1500 and 1800 nm with an estimated injection level of ∼1013 cm–3 were selected to measure the orientation-specific carrier lifetimes. The carrier lifetime was increased from 390 ns to 565 ns for (100)Ge and from 260 ns to 440 ns for (110)Ge orientations with passivation, whereas the carrier lifetime is almost unchanged for (111)Ge after passivation. This behavior indicates a strong dependence of the measured lifetime on surface orientation and surface passivation. The observed increase (>1.5×) in lifetime with Al2O3-passivated (100)Ge and (110)Ge surfaces is due to the lower surface recombination velocity compared to unpassivated Ge/AlAs heterostructures. The enhancement of carrier lifetime from passivated Ge/AlAs heterostructures with (100)Ge and (110)Ge surface orientations offers a path for the development of nanoscale transistors due to the reduced interface state density.

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High-κ Gate Dielectric on Tunable Tensile Strained Germanium Heterogeneously Integrated on Silicon: Role of Strain, Process, and Interface States

Hudait,

Clavel,

Karthikeyan

et al. 2023

ACS Appl. Electron. Mater.

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Tensile strained germanium (ε-Ge) layers heterogeneously integrated on Si substrates are of technological importance for nanoscale transistors and photonics. In this work, the tunable tensile strained (0% to 1.2%) ε-Ge layers were grown by solid source molecular beam epitaxy using GaAs and linearly graded In x Ga1–x As as intermediate buffers, and their structural and metal-oxide semiconductor capacitor (MOS-Cs) properties were analyzed as a function of strain and process conditions. X-ray topography measurements displayed no visible thermal crack and a low thermal stress of ∼50 MPa. Temperature dependent strain relaxation properties, studied by X-ray and Raman analyses, confirmed that the tensile strain amount of 1.2% was well preserved within the ε-Ge layer when annealed up to 550 °C. Further, transmission electron microscopic study revealed a good quality 1.2% strained ε-Ge/In0.17Ga0.83As heterointerface. In addition, unstrained Ge (0% ε-Ge) MOS-Cs with atomic layer deposited Al2O3 and thermally grown GeO2 composite gate dielectrics of varying oxidation times (0.25–7.5 min) at 550 °C exhibited a low interface state density (D it) of ∼2.5 × 1011 eV–1 cm–2 at 5 min oxidation duration. The minimum oxidation time needed for good capacitance–voltage (C–V) characteristics on 0.2% ε-Ge is inadequate to accomplish similar C–V characteristics on 1.2% ε-Ge MOS-C, due to the higher strain field impeding the formation of the GeO2 interface passivation layer at lower oxidation duration. In addition, with the trade-off between the minimum D it and minimum equivalent oxide thickness values, ∼1.5 min is found to be an optimum oxidation time for good quality 1.2% ε-Ge MOS-C. The minimum D it values of 1.36 × 1011 and 2.06 × 1011 eV–1 cm–2 for 0.2% and 1.2% ε-Ge, respectively, were determined for 4 nm Al2O3 with 5 min thermal oxidation at 550 °C. Therefore, the successful monolithic integration of tunable tensile strain Ge on Si with structural defects and MOS-Cs analyses offer a path for the development of tensile strained Ge-based nanoscale transistors.

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Stacked Ge Nanosheet GAAFETs Fabrication and Strain Effects Measurement

Cited by 4 publications

References 0 publications

Germanium Nanosheet-FETs Scaled to Subnanometer Node Utilizing Monolithically Integrated Lattice Matched Ge/AlAs and Strained Ge/InGaAs

Germanium Nanosheet-FETs Scaled to Subnanometer Node Utilizing Monolithically Integrated Lattice Matched Ge/AlAs and Strained Ge/InGaAs

Carrier Recombination Dynamics of Surface-Passivated Epitaxial (100)Ge, (110)Ge, and (111)Ge Layers by Atomic Layer Deposited Al₂O₃

High-κ Gate Dielectric on Tunable Tensile Strained Germanium Heterogeneously Integrated on Silicon: Role of Strain, Process, and Interface States

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Stacked Ge Nanosheet GAAFETs Fabrication and Strain Effects Measurement

Cited by 4 publications

References 0 publications

Germanium Nanosheet-FETs Scaled to Subnanometer Node Utilizing Monolithically Integrated Lattice Matched Ge/AlAs and Strained Ge/InGaAs

Germanium Nanosheet-FETs Scaled to Subnanometer Node Utilizing Monolithically Integrated Lattice Matched Ge/AlAs and Strained Ge/InGaAs

Carrier Recombination Dynamics of Surface-Passivated Epitaxial (100)Ge, (110)Ge, and (111)Ge Layers by Atomic Layer Deposited Al2O3

High-κ Gate Dielectric on Tunable Tensile Strained Germanium Heterogeneously Integrated on Silicon: Role of Strain, Process, and Interface States

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Carrier Recombination Dynamics of Surface-Passivated Epitaxial (100)Ge, (110)Ge, and (111)Ge Layers by Atomic Layer Deposited Al₂O₃