Stacked Ge-Nanosheet GAAFETs Fabricated by Ge/Si Multilayer Epitaxy

Chu, Chun-Lin; Wu, K.; Luo, Guang-Li; Chen, Bo‐Yuan; Chen, Shih-Hong; Wu, Wen−Fa; Yeh, Wen–Kuan

doi:10.1109/led.2018.2850366

Cited by 59 publications

(29 citation statements)

References 13 publications

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“…Furthermore, a larger I ON / I OFF ratio and smaller values of SS s and DIBL s for 25.8 nm- L g devices is achieved for the fabricated stacked GAA Si NS devices by the optimization of suppression of parasitic channels and device’s structure. The results indicated that the stacked GAA Si NS devices fabricated have much better comprehensive characteristics compared with those of the compared devices reported [ 10 , 11 , 12 , 13 , 30 ].…”

Section: Resultsmentioning

confidence: 86%

“…In order to achieve a compatible fabrication approach with the mainstream FinFET process and improve the driving ability of the GAA NW/NS devices, stacked GAA Si NW/NS FETs have been proposed using conventional gate-last process, which provides a simple integration method by releasing NW channels from multilayer epitaxial GeSi/Si stacks in replacement high-k dielectric/metal gate (HK/MG) trenches [ 11 ]. However, compared with the traditional bulk FinFET architecture, the fabrication of stacked GAA Si NW/NS FETs suffers from a lot of challenges, such as NSs channel release, steep fin etch, inter-diffusion restriction of GeSi/Si stacks, inner spacers, and so on [ 12 , 13 ]. In addition, conventional techniques of parasitic sub-fin channel suppression, such as halo implantation for planar device and punchthrough stop (PTS) doping for bulk FinFET, are not suitable for GAA Si NW/NS devices, which need new approaches to reduce the leakage of parasitic sub-fin channel and improve device’s subthreshold characteristics [ 14 ].…”

Section: Introductionmentioning

confidence: 99%

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Optimization of Structure and Electrical Characteristics for Four-Layer Vertically-Stacked Horizontal Gate-All-Around Si Nanosheets Devices

Zhang

et al. 2021

Nanomaterials

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In this paper, the optimizations of vertically-stacked horizontal gate-all-around (GAA) Si nanosheet (NS) transistors on bulk Si substrate are systemically investigated. The release process of NS channels was firstly optimized to achieve uniform device structures. An over 100:1 selective wet-etch ratio of GeSi to Si layer was achieved for GeSi/Si stacks samples with different GeSi thickness (5 nm, 10 nm, and 20 nm) or annealing temperatures (≤900 °C). Furthermore, the influence of ground-plane (GP) doping in Si sub-fin region to improve electrical characteristics of devices was carefully investigated by experiment and simulations. The subthreshold characteristics of n-type devices were greatly improved with the increase of GP doping doses. However, the p-type devices initially were improved and then deteriorated with the increase of GP doping doses, and they demonstrated the best electrical characteristics with the GP doping concentrations of about 1 × 1018 cm−3, which was also confirmed by technical computer aided design (TCAD) simulation results. Finally, 4 stacked GAA Si NS channels with 6 nm in thickness and 30 nm in width were firstly fabricated on bulk substrate, and the performance of the stacked GAA Si NS devices achieved a larger ION/IOFF ratio (3.15 × 105) and smaller values of Subthreshold swings (SSs) (71.2 (N)/78.7 (P) mV/dec) and drain-induced barrier lowering (DIBLs) (9 (N)/22 (P) mV/V) by the optimization of suppression of parasitic channels and device’s structure.

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Section: Resultsmentioning

confidence: 86%

Section: Introductionmentioning

confidence: 99%

Optimization of Structure and Electrical Characteristics for Four-Layer Vertically-Stacked Horizontal Gate-All-Around Si Nanosheets Devices

Zhang

et al. 2021

Nanomaterials

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“…The RMG process still will work well for the 7 nm and 5 nm technology node with SiGe nanowires through selectively removing the Si sacrificial layer from the SiGe channel material [ 234 ]. Meanwhile, for technology nodes 3 nm and beyond, the sacrificial material is SiGe and will be selectively removed from Ge channel [ 235 , 236 , 237 ].…”

Section: Wet Cleaningmentioning

confidence: 99%

State of the Art and Future Perspectives in Advanced CMOS Technology

et al. 2020

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The international technology roadmap of semiconductors (ITRS) is approaching the historical end point and we observe that the semiconductor industry is driving complementary metal oxide semiconductor (CMOS) further towards unknown zones. Today’s transistors with 3D structure and integrated advanced strain engineering differ radically from the original planar 2D ones due to the scaling down of the gate and source/drain regions according to Moore’s law. This article presents a review of new architectures, simulation methods, and process technology for nano-scale transistors on the approach to the end of ITRS technology. The discussions cover innovative methods, challenges and difficulties in device processing, as well as new metrology techniques that may appear in the near future.

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“…In recent years, with the continuous scaling-down of CMOS technology nodes, high-mobility channel materials (SiGe, Ge and III–V material such as InGaAs) and novel device designs (horizontally/vertically Gate-All-Around (GAA) stacked nanowires) have been under investigation [ 1 , 2 , 3 , 4 , 5 , 6 , 7 , 8 , 9 , 10 , 11 , 12 , 13 ]. The high mobility of n-GaN and the current possibility of achieving an enhancement mode in non-polar GaN have also been extensively researched with gallium nitride Fin Field-Effect Transistors (FinFETs) [ 14 , 15 ].…”

Section: Introductionmentioning

confidence: 99%

Strained Si0.2Ge0.8/Ge multilayer Stacks Epitaxially Grown on a Low-/High-Temperature Ge Buffer Layer and Selective Wet-Etching of Germanium

et al. 2020

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With the development of new designs and materials for nano-scale transistors, vertical Gate-All-Around Field Effect Transistors (vGAAFETs) with germanium as channel materials have emerged as excellent choices. The driving forces for this choice are the full control of the short channel effect and the high carrier mobility in the channel region. In this work, a novel process to form the structure for a VGAA transistor with a Ge channel is presented. The structure consists of multilayers of Si0.2Ge0.8/Ge grown on a Ge buffer layer grown by the reduced pressure chemical vapor deposition technique. The Ge buffer layer growth consists of low-temperature growth at 400 °C and high-temperature growth at 650 °C. The impact of the epitaxial quality of the Ge buffer on the defect density in the Si0.2Ge0.8/Ge stack has been studied. In this part, different thicknesses (0.6, 1.2 and 2.0 µm) of the Ge buffer on the quality of the Si0.2Ge0.8/Ge stack structure have been investigated. The thicker Ge buffer layer can improve surface roughness. A high-quality and atomically smooth surface with RMS 0.73 nm of the Si0.2Ge0.8/Ge stack structure can be successfully realized on the 1.2 µm Ge buffer layer. After the epitaxy step, the multilayer is vertically dry-etched to form a fin where the Ge channel is selectively released to SiGe by using wet-etching in HNO3 and H2O2 solution at room temperature. It has been found that the solution concentration has a great effect on the etch rate. The relative etching depth of Ge is linearly dependent on the etching time in H2O2 solution. The results of this study emphasize the selective etching of germanium and provide the experimental basis for the release of germanium channels in the future.

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Stacked Ge-Nanosheet GAAFETs Fabricated by Ge/Si Multilayer Epitaxy

Cited by 59 publications

References 13 publications

Optimization of Structure and Electrical Characteristics for Four-Layer Vertically-Stacked Horizontal Gate-All-Around Si Nanosheets Devices

Optimization of Structure and Electrical Characteristics for Four-Layer Vertically-Stacked Horizontal Gate-All-Around Si Nanosheets Devices

State of the Art and Future Perspectives in Advanced CMOS Technology

Strained Si0.2Ge0.8/Ge multilayer Stacks Epitaxially Grown on a Low-/High-Temperature Ge Buffer Layer and Selective Wet-Etching of Germanium

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