Stable, Reliable, and Bit-Interleaving 12T SRAM for Space Applications: A Device Circuit Co-Design

Yadav, Nandakishor; Shah, Ambika Prasad; Vishvakarma, Santosh Kumar

doi:10.1109/tsm.2017.2718029

Cited by 54 publications

(28 citation statements)

References 36 publications

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“…On the other hand, the WWL12T/D12T cell consumes higher area 1.06 × /1.04 × when compared to WALP11T due to the presence of an additional NMOS transistor. Table 1 reports the comparison of the proposed WALP11T cell, in terms of major design metrics, with the previously proposed FD8T [11], BI11T [12], SEDF9T [15], WWL12T [23] and D12T [24] cells as well as additional state-of-the-art SRAM cells such as transmission-gate based 9T (TG9T) [32], power-gated 9T (PG9T) [33], differential writing 10T (10T-P1) [34] and feedback-cutting 11T (FC11T) [35] at V DD = 0.3 V. As is evident, the WALP11T cell shows shorter T RA than most other cells used in this work. However, the FD8T shows shorter T RA than the proposed cell due to its higher β-ratio and its structural similarity to the conventional 6T cell.…”

Section: Layout Areamentioning

confidence: 99%

“…Table 1 reports the comparison of the proposed WALP11T cell, in terms of major design metrics, with the previously proposed FD8T [11], BI11T [12], SEDF9T [15], WWL12T [23] and D12T [24] cells as well as additional state‐of‐the‐art SRAM cells such as transmission‐gate based 9T (TG9T) [32], power‐gated 9T (PG9T) [33], differential writing 10T (10T‐P1) [34] and feedback‐cutting 11T (FC11T) [35] at

V_{DD} = 0.3 normalV

. As is evident, the WALP11T cell shows shorter

T_{RA}

than most other cells used in this work.…”

Section: Comparison Summarymentioning

confidence: 99%

“…On the contrary, the isolation of storage nodes from bitlines in the read‐decoupled cells proposed in [12, 14, 21, 22] and the SEDF9T [15] leads to significant improvement in read stability. The self‐refreshing logic‐based 12T (WWL12T) [23] cell (see Fig. 3), in particular, consists of an additional pair of transmission gates (TG1 and TG2) in its access path to refresh the stored data.…”

Section: Introductionmentioning

confidence: 99%

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Reliable write assist low power SRAM cell for wireless sensor network applications

Pal

Bose

et al. 2020

IET Circuits, Devices & Systems

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In this study, the authors have proposed a Write Assist Low Power 11T (WALP11T) SRAM cell. To analyse its performance in terms of major design metrics, the proposed cell has been compared with contemporary SRAMs like the Fully Differential 8T (FD8T), Single-Ended Disturb Free 9T (SEDF9T), Bit-interleaving architecture supporting 11T (BI11T), Selfrefreshing Logic-based 12T (WWL12T) and Differential 12T (D12T) cells. The proposed cell exhibits significantly shorter read/ write delay when compared to most comparison cells. It shows considerably higher read stability and write ability than that of FD8T and SEDF9T/D12T/WWL12T, respectively. Moreover, WALP11T dissipates significantly lower leakage power in comparison to the majority of comparison cells and exhibits 2.21 × /1.18 × lower read power delay product (R PDP) than that of BI11T/D12T and 5.12 × /1.39 × /1.09 × lower write power delay product (W PDP) than that of BI11T/WWL12T/D12T. The proposed cell consumes considerably lower area than WWL12T/D12T and shows highly reliable operation when subjected to the harsh process, voltage and temperature variations at both Slow NMOS-Fast PMOS and Fast NMOS-Slow PMOS corners. For all these improvements, WALP11T shows longer read/write delay than FD8T, higher leakage power and power delay product than BI11T and FD8T/SEDF9T, respectively, at V DD = 0.3 V.

show abstract

Section: Layout Areamentioning

confidence: 99%

V_{DD} = 0.3 normalV

. As is evident, the WALP11T cell shows shorter

T_{RA}

than most other cells used in this work.…”

Section: Comparison Summarymentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Reliable write assist low power SRAM cell for wireless sensor network applications

Pal

Bose

et al. 2020

IET Circuits, Devices & Systems

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show abstract

“…Radiation hardening by design (RHBD) is one of the most effective techniques to mitigate soft errors. In the last decade, researchers have mostly focused on the radiation hardening for memory cells [4,5], flip-flops [6,7] and latches [1,[8][9][10][11][12][13][14][15][16][17][18][19][20][21] using RHBD techniques like multiplemodular redundancy, temporal redundancy, and so on. This paper mainly focuses on these latch designs.…”

Section: Introductionmentioning

confidence: 99%

Novel Low Cost, Double-and-Triple-Node-Upset-Tolerant Latch Designs for Nano-scale CMOS

Yan

Lai

Zhang

et al. 2021

IEEE Trans. Emerg. Topics Comput.

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This paper presents two novel low cost, double-and-triple-node-upset tolerant latch designs. First, a novel low cost and double-node-upset (DNU) completely tolerant (LCDNUT) latch design is proposed. The latch mainly comprises a storage module (SM) feeding back to a 3-input C-element. The SM mainly consists of eight input-split inverters. Since the inputs of the C-element cannot be simultaneously flipped, the latch tolerates any DNU in the SM. When a single node in the SM and the output node are affected, the latch can self-recover from the DNU. Second, to completely tolerate any triple-node-upset (TNU), by replacing the C-element in the LCDNUT latch with a two-level error-interceptive module constructed from triple C-elements, a novel low cost and TNU completely tolerant (LCTNUT) latch design is proposed. Simulation results demonstrate the robustness of the proposed latches. Furthermore, due to the use of a high-speed transmission path, the clock-gating technology and fewer transistors, the proposed LCTNUT latch reduces the delay-power-area product by approximately 99.39% and has a low sensitivity to the process-voltage-and-temperature variation effects, compared with currently the only TNU completely tolerant latch design.

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“…To mitigate SNUs, DNUs, TNUs, and/or SETs, by means of radiation-hardening-by-design (RHBD) approaches, many hardened storage cells such as static random access memories (SRAMs) [9][10][11][12], flip-flops [13][14][15][16], and latches [5][6][7][8][17][18][19][20][21][22][23][24][25][26][27], have been proposed. This paper focuses on latches.…”

Section: Introductionmentioning

confidence: 99%

HITTSFL: Design of a Cost-Effective HIS-Insensitive TNU-Tolerant and SET-Filterable Latch for Safety-Critical Applications

Yan

Feng

Zhao

et al. 2020

2020 57th ACM/IEEE Design Automation Conference (DAC)

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This paper proposes a cost-effective, high-impedancestate (HIS)-insensitive, triple-node-upset (TNU)-tolerant and single-event-transient (SET)-filterable latch, namely HITTSFL, to ensure high reliability with low-cost. The latch mainly comprises an output-level SET-filterable Schmitt-trigger and three inverters that make the values stored in three parallel single-node-upset (SNU)-recoverable dual-interlocked-storagecells (DICEs) converge at a common node to tolerate any possible TNU. The latch does not use C-elements to be insensitive to the HIS. Simulation results demonstrate the TNU-tolerability and SET-filterability of the proposed HITTSFL latch. Moreover, due to the use of clock-gating technologies and fewer transistors, the proposed latch can reduce delay, power, and area by 76.65%, 6.16%, and 28.55%, respectively, compared with the state-of-theart TNU hardened latch (TNUHL) that cannot filter SETs.

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Stable, Reliable, and Bit-Interleaving 12T SRAM for Space Applications: A Device Circuit Co-Design

Cited by 54 publications

References 36 publications

Reliable write assist low power SRAM cell for wireless sensor network applications

Reliable write assist low power SRAM cell for wireless sensor network applications

Novel Low Cost, Double-and-Triple-Node-Upset-Tolerant Latch Designs for Nano-scale CMOS

HITTSFL: Design of a Cost-Effective HIS-Insensitive TNU-Tolerant and SET-Filterable Latch for Safety-Critical Applications

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