SrTiOx for sub-20nm DRAM technology nodes—Characterization and modeling

Abstract

The electrical properties of Ru/SrTiO/Ru capacitors have been investigated. EOT of 0.38 nm at VG = 0 V and JG ~ 10 -7 Acm -2at VG = ±1V and temperature T = 25 o C meet sub-20 nm DRAM requirements. Relaxation measurements were performed, indicating acceptable charge loss. Modeling of defects based on multi-phonon trap-assisted-tunneling SrTiO can quantitavely well describe leakage and capacitance behavior.

(Invited) Defect Spectroscopy and Engineering for Nanoscale Electron Device Applications: A Novel Simulation-Based Methodology

“…The large amount of dynamic RAM required by the modern software architecture and the rigid scaling constraints imposed by ITRS for sub-20nm technological nodes (26). Storage MIM capacitor requires to deal with novel materials (e.g.…”

A Technology-Computer-Aided-Design-Based Reliability Prediction Model for DRAM Storage Capacitors

“…For the first approach, storage capacitors are converted from planar into three-dimensional (3D) structures to maximize their aspect ratios [3]. Regarding the second approach, various types of high- k materials are introduced such as ZrO 2 [4], TiO 2 [5], and SrTiO [6], which tends to deteriorate the defect density and bandgap energy [7]. This implies that state-of-the-art DRAM storage capacitors suffer from reliability issues such as leakage current and time-dependent dielectric breakdown (TDDB) [8].…”

Asymmetric dual-gate-structured one-transistor dynamic random access memory cells for retention characteristics improvement

“…As conventional one-transistor (1T) one-capacitor DRAM cells are scaled down, reducing capacitor volume has become one of the major challenges. [1][2][3][4][5] According to International Technology Roadmap for Semiconductors 2013, the half-pitch size of DRAM cells will be less than 10 nm by 2025; however, it would be limited because capacitors with high-aspect-ratio trenches can lean into each other. 6) To solve this physical problem, many studies have focused on 1T-DRAM devices in recent years, which are DRAM cells composed of a single transistor on a silicon-on-insulator (SOI) wafer.…”