Asymmetric dual-gate-structured one-transistor dynamic random access memory cells for retention characteristics improvement

Abstract

One of the major concerns of one-transistor dynamic random access memory (1T-DRAM) is poor retention time. In this letter, a 1T-DRAM cell with two separated asymmetric gates was fabricated and evaluated to improve sensing margin and retention characteristics. It was observed that significantly enhanced sensing margin and retention time over 1 s were obtained using a negatively biased second gate and trapped electrons in the nitride layer because of increased hole capacity in the floating body. These findings indicate that the proposed device could serve as a promising candidate for overcoming retention issues of 1T-DRAM cells.

Grain boundary induced short-term memory effect in fully depleted thin-polysilicon devices

“…Moreover, the drain current difference between the two pulses can be interpreted as the sensing margin of 1T-DRAM operation. 6,23,24) The inset of Fig. 4 indicates that the sensing margin of the FD polysilicon transistor was about 400 μs.…”

“…In order to overcome the disadvantages inherent in DRAMs, a 1T-DRAM using only one transistor without a capacitor was proposed. [1][2][3][4][5][6][7][8][9][10] 1T-DRAM utilizes the floating body effect (FBE) to use a floating body as a memory storage node. The FBE is a phenomenon that occurs in a transistor using a Si-on-insulator (SOI) structure, in which holes generated by impact ionization on the drain side cannot immediately sink to the source and accumulate on the floating body.…”

Combination of volatile and non-volatile functions in a single memory cell and its scalability

“…The fabrication details have been described elsewhere. [27][28][29] 3. Results and discussion 3.1 Memory functions Figure 3(a) shows the measured transfer curve of the G2 after program and erase operations of the NVM function, and there is obvious threshold voltage (V T ) shift made by applying the G2 voltage (V G2 ) of 15 V for 0.1 ms and −15 V for 1 ms, respectively.…”

Silicon synaptic transistor for hardware-based spiking neural network and neuromorphic system

“…The second CMP was done after the fin formation using 50 nm of SiO 2 sidewall and deposition of G2 gate stack. The more-detailed description of the process method has been described elsewhere [40][41][42]. The G1 with a single SiO 2 layer is used to receive signals from pre-synaptic neuron circuit and the second gate (G2) with oxide-nitride-oxide stacks is used to receive signals from post-synaptic one and store charges in its nitride layer.…”

“…The shifted transfer curves obtained by applying pre-and post-synaptic spikes 10 times while keeping Δt as 0.5 and −0.5 μs are plotted in figure 5(a). The retention characteristics of multiple threshold voltage (V T ) states induced by trapped carriers in G2 stack were demonstrated in [41]. The amount of threshold voltage change (ΔV T ) per a spike becomes smaller when those spikes are applied to the device repeatedly, meaning that V T modulation amount at the same Δt condition can differ when the synaptic transistor is learned in one direction, potentiation or depression.…”