Combination of volatile and non-volatile functions in a single memory cell and its scalability

Abstract

A single memory cell which combines volatile memory and non-volatile memory functions has been demonstrated with an independent asymmetric dual-gate structure. Owing to the second gate whose dielectric is composed of oxide/nitride/oxide layers, floating body effect was observed even on a fully depleted silicon-on-insulator device and the non-volatile memory function was measured. In addition, read retention characteristics of the volatile memory function depending on the non-volatile memory state were evaluated and analyzed. Further scalability in body thickness was also verified through simulation studies. These results indicate that the proposed device is a promising candidate for high-density embedded memory applications.

Grain boundary induced short-term memory effect in fully depleted thin-polysilicon devices

“…Moreover, the drain current difference between the two pulses can be interpreted as the sensing margin of 1T-DRAM operation. 6,23,24) The inset of Fig. 4 indicates that the sensing margin of the FD polysilicon transistor was about 400 μs.…”

Comparison of writing methods of single memory cell with volatile and nonvolatile memory functions

“…1(a). 17) In this present study, two writing methodsimpact ionization (II) and gate-induced drain leakage (GIDL)for the VM function are compared with regard to the sensing margin of the VM function and the soft-programming issues in the NVM function. The sensing margin of the VM function is significantly enhanced when the GIDL method is used because the trapped electrons increase the band-to-band generation rate.…”