Silicon synaptic transistor for hardware-based spiking neural network and neuromorphic system

Abstract

Brain-inspired neuromorphic systems have attracted much attention as new computing paradigms for power-efficient computation. Here, we report a silicon synaptic transistor with two electrically independent gates to realize a hardware-based neural network system without any switching components. The spike-timing dependent plasticity characteristics of the synaptic devices are measured and analyzed. With the help of the device model based on the measured data, the pattern recognition capability of the hardware-based spiking neural network systems is demonstrated using the modified national institute of standards and technology handwritten dataset. By comparing systems with and without inhibitory synapse part, it is confirmed that the inhibitory synapse part is an essential element in obtaining effective and high pattern classification capability.

Solving Overlapping Pattern Issues in On-Chip Learning of Bio-Inspired Neuromorphic System with Synaptic Transistors

“…where α is a fitting coefficient. The type and number of injected carriers are determined depending on V G2 so that the amount of V T change (∆V T ) per each pre-and post-synaptic spike is calculated, providing good agreement with the measured data [28]. Technology (MNIST) handwritten dataset.…”

“…In our previous works, we reported a synaptic transistor with an asymmetric dual-gate structure as having short-and long-term memories and spike-timing dependent plasticity (STDP) characteristics [26][27][28], and its fabrication method [29]. In this work, a system-level study of a SNN for pattern recognition is presented with a binary modified National Institute of Standards and Technology (MNIST) handwritten dataset.…”

Impact of the Sub-Resting Membrane Potential on Accurate Inference in Spiking Neural Networks

“…As shown in Fig. 4b, we propose an I&F neuron circuit which differs from the conventional I&F neuron circuit proposed earlier by the authors in that the newly proposed circuit can maintain the NMP 36,37 . Generally, CMOS I&F neurons are composed of current mirrors, a capacitor, and cascaded inverters.…”

Artificial 2D van der Waals Synapse Devices via Interfacial Engineering for Neuromorphic Systems

“…This has motivated the exploration of novel computation systems beyond the conventional Von Neumann architecture that can overcome the downscaling limitations. Recently, due to the increasing need to implement sophisticated information processing system mimicking the human brain, the neuromorphic computing system has attracted a great deal of attention [1][2][3][4][5]. For the integrated neuromorphic systems, it is important to realize operations of complex and diverse functions implemented using a parallel architecture consisting of~10 11 neurons and~10 15 synapses.…”