Speculative hardware/software co-designed floating-point multiply-add fusion

Lupon, Marc; Gibert, Enric; Magklis, Grigorios; Samudrala, S.; Martínez, Rosario de Vicente; Stavrou, Kyriakos; Ditzel, David R.

doi:10.1145/2541940.2541978

Cited by 12 publications

(4 citation statements)

References 27 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Singh et al [33] focused on instruction fusion, exploring opportunities for fusing additional instructions in a high-performance general purpose pipeline. Lupon et al [34] used DBT with slight modifications to an FMA unit, and achieved the fusion of FP multiply and FP add to produce an FP multiply-add instruction. However, these co-design methods primarily require synchronous modifications.…”

Section: Related Workmentioning

confidence: 99%

Performance Improvements via Peephole Optimization in Dynamic Binary Translation

Xie,

Luo,

Tian

et al. 2024

Electronics

View full text Add to dashboard Cite

The emergence of new instruction set architectures (ISAs) poses challenges in ensuring compatibility with legacy applications. Dynamic binary translation (DBT) serves as a crucial approach for achieving cross-ISA compatibility, enabling legacy applications to run compatibly with cross-ISAs. However, software-based translation encounters significant performance overhead, including substantial memory access and insufficient exploitation of target architecture features. The significant performance overhead challenges hinder the practical implementation of DBT. In this paper, we investigate a novel peephole optimization approach. First, we perform peephole analysis to identify redundant memory access and suboptimal instruction sequences. Next, we leverage live variable analysis to eliminate redundant memory-access instructions. Additionally, we bridge the gaps between cross-ISAs by exploiting ISA-specific features through instruction fusion. Finally, we implement the proposed optimization design using the open-source QEMU and extensively evaluate it on both ARM64 and SW64 platforms. The experimental results reveal that SPEC2006 benchmark effectively gets a maximum performance speedup of 1.52×, alongside a reduction in code size of up to 13.98%. These results affirm the effectiveness of our optimization approach in DBT performance and code sizes.

show abstract

Section: Related Workmentioning

confidence: 99%

Performance Improvements via Peephole Optimization in Dynamic Binary Translation

Xie,

Luo,

Tian

et al. 2024

Electronics

View full text Add to dashboard Cite

show abstract

“…In addition, there have been FMA units with modi¯ed pipeline structure to improve program throughput, 9 and hardware/software co-designed FMA units to reuse existing executable binaries. 10 The third category has been dedicated to study FMA architecture to accelerate speci¯c applications such as 4D graphics, 11 decimal°oating-point arithmetic, 12,13 and Software De¯ned Radio (SDR). 14 Latest FMA-related studies span through the second and the third categories.…”

Section: Related Workmentioning

confidence: 99%

Proxy Bits for Low Cost Floating-Point Fused Multiply–Add Unit

Kim

Moon

2016

J CIRCUIT SYST COMP

View full text Add to dashboard Cite

A new°oating-point fused multiply-add (FMA) unit is proposed in this paper. We observed a group of redundant bits that have no e®ect on the e®ective results of the°oating-point FMA arithmetic, and¯gured out that two proxy bits can replace the redundant bits. We proved the existence of the proxy bits using binary arithmetic keeping track of the negligible bits. Using proxy bits, the proposed FMA unit achieves improvement in terms of cost, power consumption, and performance. The results show that the proposed FMA unit reduces the total area and latency by approximately 17.0% and 32% respectively, compared with a current widely used FMA unit.

show abstract

“…Earlier examples include Transmeta products Crusoe [1], [2] and Efficeon [3], as well as research projects from IBM like DAISY [4] and BOA [5]. Currently, there is a renewed interest from both industry [6], [7] and academia [8], [9], [10], [11], [12], [13]. The fundamental idea behind all these systems is to have a simple host ISA to achieve design simplicity and energy efficiency.…”

Section: Introductionmentioning

confidence: 99%

Quantitative characterization of the software layer of a HW/SW co-designed processor

Cano

Kumar

Brankovic

et al. 2016

2016 IEEE International Symposium on Workload Characterization (IISWC)

Self Cite

View full text Add to dashboard Cite

Abstract-HW/SW co-designed processors currently have a renewed interest due to their capability to boost performance without running into the power and complexity walls. By employing a software layer that performs dynamic binary translation and applies aggressive optimizations through exploiting the runtime application behavior, these hybrid architectures provide better performance/watt. However, a poorly designed software layer can result in significant translation/optimization overheads that may offset its benefits. This work presents a detailed characterization of the software layer of a HW/SW co-designed processor using a variety of benchmark suites. We observe that the performance of the software layer is very sensitive to the characteristics of the emulated application with a variance of more than 50%. We also show that the interaction between the software layer and the emulated application, while sharing the microarchitectural resources, can have 0-20% impact on performance. Finally, we identify some key elements which should be further investigated to reduce the observed variations in performance. The paper provides critical insights to improve the software layer design.

show abstract

Speculative hardware/software co-designed floating-point multiply-add fusion

Cited by 12 publications

References 27 publications

Performance Improvements via Peephole Optimization in Dynamic Binary Translation

Performance Improvements via Peephole Optimization in Dynamic Binary Translation

Proxy Bits for Low Cost Floating-Point Fused Multiply–Add Unit

Quantitative characterization of the software layer of a HW/SW co-designed processor

Contact Info

Product

Resources

About