A new°oating-point fused multiply-add (FMA) unit is proposed in this paper. We observed a group of redundant bits that have no e®ect on the e®ective results of the°oating-point FMA arithmetic, and¯gured out that two proxy bits can replace the redundant bits. We proved the existence of the proxy bits using binary arithmetic keeping track of the negligible bits. Using proxy bits, the proposed FMA unit achieves improvement in terms of cost, power consumption, and performance. The results show that the proposed FMA unit reduces the total area and latency by approximately 17.0% and 32% respectively, compared with a current widely used FMA unit.
In recent years, the development of multimedia devices has meant that a wider multimedia streaming service can be supported, and there are now many ways in which TV channels can communicate with different terminals. Generally, scalable video streaming is known to provide more efficient channel capacity than simulcast video streaming. Simulcast video streaming requires a large network bandwidth for all resolutions, but scalable video streaming needs only one flow for all resolutions. In previous research, scalable video streaming has been compared with simulcast video streaming for network channel capacity, in two user simulation environments. The simulation results show that the channel capacity of SVC is 16% to 20% smaller than AVC, but scalable video streaming is not efficient because of the limit of the present network framework. In this paper, we propose a new network framework with an SVC extractor. The proposed network framework shows a channel capacity 50% (maximum) lower than that found in previous research studies.
In this study, we propose a radix-16 Booth multiplier using a novel weighted 2-stage Booth algorithm. Most conventional multipliers utilize radix-4 Booth encoding because a higher radix increases encoder complexity. To resolve this problem, we propose the weighted 2-stage Booth algorithm. The synthesis results show that the multiplier using the proposed algorithm achieves better power-delay products than those achieved by conventional Booth multipliers. We believe that the proposed Booth algorithm can be broadly utilized in general processors as well as digital signal processors, mobile application processors, and various arithmetic units that use Booth encoding.
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